Trench Gate Oxide Structure for GIDL Reduction
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Solution Overview
Problem
As semiconductor devices integrate more densely, the short channel effect and gate-induced drain leakage (GIDL) due to reduced gate oxide thickness degrade refresh characteristics and increase power consumption, particularly in DRAMs.
Innovation Solution
A semiconductor device with a trench structure featuring a thicker first gate oxide layer and a thinner second gate oxide layer, along with a spacer pattern and junction region, is manufactured to prevent GIDL by inhibiting leakage between the buried gate and junction region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the gate oxide layer thickness is reduced to improve gate controllability, then gate controllability is improved, but gate induced drain leakage (GIDL) increases due to electric field concentration
Solution Approach 1:
The patent applies local quality by creating a multi-layer gate oxide structure where the first gate oxide layer has a different thickness than the second gate oxide layer. Specifically, the first gate oxide layer is positioned in the overlap region between the gate and junction, while the second gate oxide layer is positioned elsewhere. This local variation in oxide thickness allows the first layer to reduce GIDL by providing adequate insulation in the high electric field region, while the second layer maintains gate controllability where needed.
Solution Approach 2:
The gate oxide layer is segmented into two distinct layers: a first gate oxide layer and a second gate oxide layer. This segmentation allows each layer to serve different functional purposes - the first layer addresses GIDL in the overlap region while the second layer provides overall gate insulation and controllability. The segmentation resolves the contradiction by distributing the functional requirements across multiple specialized sub-structures.
2Manufacturing precision
If the gate oxide layer thickness is reduced to improve manufacturing precision, then manufacturing precision is improved, but refresh characteristics degrade due to increased leakage current
Solution Approach 1:
The patent implements local quality by positioning the first gate oxide layer with greater thickness specifically in the overlap region where GIDL occurs, while the second gate oxide layer has reduced thickness in other regions. This localized thickness variation maintains reliable insulation where needed to prevent leakage and preserve refresh characteristics, while allowing thinner oxide elsewhere to improve manufacturing precision and gate controllability.
3Object-generated harmful factors
If high dielectric material layer is used to reduce gate leakage current, then gate leakage current is reduced, but etch selectivity between metal layer and high dielectric material layer decreases
Solution Approach 1:
The patent uses composite materials by combining a high dielectric material layer (such as hafnium oxide or hafnium silicon oxide) with a metal layer to form the gate structure. This composite structure reduces gate leakage current through the high dielectric properties while the specific layer configuration and material selection help manage etch selectivity issues during manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces GIDL, enhancing refresh characteristics and minimizing parasitic capacitance, thereby improving the performance and reliability of semiconductor devices.
Implementation Method 1
a first gate oxide layer disposed between the spacer pattern and the trench, a second gate oxide layer disposed below the first gate oxide layer and the gate metal
Implementation Method 2
an electric field is concentrated at an area between the gates thus causing gate induced drain leakage (GIDL)... The first gate oxide layer may have a thicker thickness than the second gate oxide layer
Data Source
AI summary
A semiconductor device includes a gate metal buried within a trench included in a semiconductor substrate including an active region defined by an isolation layer, a spacer pattern disposed on an upper portion of a sidewall of a gate metal, a first gate oxide layer disposed between the spacer pattern and the trench, a second gate oxide layer disposed below the first gate oxide layer and the gate metal, and a junction region disposed in the active region to overlap the first gate oxide layer.