Trench Gate Select Transistor for NAND Flash Scaling
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Solution Overview
Problem
The scaling of gate length for select gate transistors in nonvolatile semiconductor memory devices, such as NAND flash memory, is more difficult than for memory cell transistors, limiting the reduction in device area due to insufficient channel voltage cutoff and potential reliability issues with electric field concentration and gate insulation.
Innovation Solution
The implementation of a trench structure for select gate transistors, where at least part of the gate electrode is formed on the sidewalls of a trench in the substrate, allowing for increased gate length in the vertical direction and enabling scaling of gate length in the horizontal direction without degrading cutoff characteristics, thereby reducing the device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate length of select gate transistor is decreased by scaling to reduce device area, then area is reduced, but channel voltage cutoff becomes insufficient and reliability deteriorates
Solution Approach 1:
The gate electrode is extended into the vertical dimension by forming it on the sidewalls of a trench structure. This allows the gate length to have significant vertical component while the horizontal footprint is reduced, enabling area scaling without sacrificing voltage cutoff capability.
Solution Approach 2:
The gate electrode is nested within the trench structure formed in the substrate. The trench provides a confined space that guides the gate electrode configuration, allowing the gate to be positioned precisely where needed to control the channel while occupying minimal horizontal space.
2Area of stationary object
If the gate length of select gate transistor is decreased by scaling, then device area is reduced, but short-channel effects become more severe
Solution Approach 1:
By transitioning from a planar gate structure to a three-dimensional sidewall gate structure, the invention introduces vertical control dimension. This allows the effective gate length to be sufficiently long in the vertical direction to control short-channel effects while maintaining small horizontal dimensions for area reduction.
Solution Approach 2:
The gate electrode is positioned specifically on the sidewalls of the trench where it is most needed for channel control. This localized placement optimizes the electric field distribution to suppress short-channel effects at the critical channel region while minimizing overall device footprint.
3Area of stationary object
If the gate length of select gate transistor is decreased by scaling, then device area is reduced, but electric field concentration and gate insulation reliability worsen
Solution Approach 1:
The trench structure distributes the electric field control into the vertical dimension, preventing excessive concentration in the horizontal plane. The sidewall configuration allows the electric field to be more uniformly distributed along the channel length, reducing hot spots and improving gate insulation reliability.
Solution Approach 2:
The trench structure acts as an intermediary that mediates between the gate electrode and the channel. It provides a controlled environment that shapes and distributes the electric field, preventing direct concentration at critical points while maintaining effective channel control.
Data Source
AI summary
A nonvolatile semiconductor memory device includes a plurality of memory cell units and a memory cell array in which the memory cell units are arranged in matrix. Each of the memory cell units has a given number of electrically writable and erasable memory cell transistors that are connected in a column direction to form a memory cell column. One end of the memory cell column is connected to a bit line via a first select gate transistor, and the other end thereof is connected to a source line via a second select gate transistor. At least part of a gate electrode of one of the first and second select gate transistors is provided in a trench formed in the surface area of a substrate along a direction parallel to a word line.