Trench Gate Semiconductor Device Void Reduction
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Solution Overview
Problem
Insulated gate semiconductor devices with trench structures face challenges in reducing on-state resistance due to voids in polycrystalline silicon-filled trenches, leading to variations in characteristics such as on-state resistance, threshold voltage, and forward voltage.
Innovation Solution
The semiconductor device incorporates a configuration with first and second trenches forming a T-shape connection, where the second trenches cross adjacent first trenches, ensuring complete filling of polycrystalline silicon and reducing voids, along with a ladder-shaped body region to enhance gate length and avalanche resistance, and a straight linkage portion for the gate lead wiring to minimize bent portions and expand the element region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If trenches are formed in stripes with source region crossing them, then the pitch of trench gates can be reduced to 1/3 of grid pattern, but voids occur in polycrystalline silicon filled into the trenches causing characteristic variations
Solution Approach 1:
The continuous trench structure is segmented by forming second trenches that intersect the first trenches, dividing the polycrystalline silicon filling process into manageable sections. This segmentation allows complete filling at intersection points, eliminating voids while maintaining the fine pitch structure.
Solution Approach 2:
The solution transitions from a one-dimensional stripe pattern to a two-dimensional grid-like pattern by adding second trenches in a perpendicular direction. This dimensional change creates intersection points that ensure complete polycrystalline silicon filling, preventing voids while maintaining reduced pitch.
2Reliability
If trench gates are formed in grid pattern, then voids are reduced, but the pitch of trench gates is larger compared to stripe pattern
Solution Approach 1:
Rather than forming a complete grid pattern, the invention selectively segments the trench structure by forming second trenches that intersect only specific first trenches. This partial segmentation reduces voids at critical intersection points while maintaining the overall reduced pitch advantage of the stripe pattern.
Solution Approach 2:
The second trenches are formed locally at specific positions to address void formation issues, rather than uniformly across the entire structure. This local quality approach maintains the fine pitch characteristics where needed while adding filling assurance only where voids occur.
3Adaptability or versatility
If gate lead wiring has bent portions, then routing flexibility is improved, but the element region area is reduced and chip size increases
Solution Approach 1:
The gate lead wiring is extracted from the element region and routed along the periphery. This separation removes the bent portions and wiring complexity from the critical element region, maximizing its area while maintaining routing flexibility in the peripheral region.
Solution Approach 2:
The gate lead wiring routing is moved from the two-dimensional element region plane to the peripheral boundary, utilizing the chip's outer perimeter space. This dimensional relocation preserves wiring flexibility without consuming element region area.
Data Source
AI summary
A gate lead wiring and an electrical conductor connecting the gate lead wiring to a protective diode are arranged in a straight line without bending along one and the same side of the chip. A first gate electrode layer extending on the gate lead wiring and the electrical conductor, which connects them to the protective diode, has one bent portion or no bent portion. Further, the protective diode is arranged adjacent to the electrical conductor or the gate lead wiring, and a portion of the protective diode is arranged in close proximity to a gate pad portion.