Trench Gate Semiconductor Device With Side Wall Insulating Layer
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Solution Overview
Problem
The existing semiconductor device manufacturing methods face challenges in maintaining the channel length and electrical characteristics, particularly due to variations in the trench structure and impurity introduction, leading to issues like increased leakage current and threshold voltage deviations.
Innovation Solution
The semiconductor device incorporates a side wall insulating layer covering the trench, allowing for controlled introduction of impurities to maintain channel length and electrical characteristics, thereby suppressing variations in electrical performance across different device formation regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If impurity is introduced into the surface layer portion without side wall insulation, then doping efficiency is improved, but channel length control deteriorates and leakage current increases
Solution Approach 1:
The patent divides the trench structure into two distinct regions: a lower region with the gate electrode and an upper recessed portion. The side wall insulating layer is selectively formed only in the recessed portion, segmenting the doping regions. This allows impurity to be introduced into the surface layer portion through side walls in the recessed area without affecting the gate electrode region, thereby controlling channel length while maintaining doping efficiency.
Solution Approach 2:
The side wall insulating layer is applied locally only to the recessed portion of the trench side walls, not the entire trench. This local application enables selective impurity introduction: the insulating layer blocks impurity near the gate electrode while allowing impurity to reach the surface layer portion through exposed side walls, achieving precise spatial control over doping regions and maintaining both channel length control and doping efficiency.
2Reliability
If gate electrode upper surface is located below main surface, then device reliability is improved, but manufacturing precision deteriorates due to variations in recessed portion depth
Solution Approach 1:
The side wall insulating layer is formed in advance during the gate electrode formation process, before impurity introduction. This preliminary action creates a protective barrier that prevents impurity from reaching deep regions regardless of variations in recessed portion depth. Even when the gate electrode upper surface is below the main surface, the pre-formed insulating layer ensures consistent channel length by blocking impurity diffusion paths.
Solution Approach 2:
The side wall insulating layer acts as a cushioning barrier against impurity diffusion. By placing this insulating layer beforehand on the trench side walls, the patent compensates for variations in recessed portion depth and gate electrode positioning. The insulating layer absorbs the variability in geometry, ensuring that impurity introduction remains controlled and channel length consistency is maintained despite manufacturing variations.
3Stability of the object's composition
If side wall insulating layer is formed in recessed portion, then channel length stability is improved, but device complexity increases
Solution Approach 1:
The patent segments the side wall treatment into two parts: the lower trench wall remains exposed for impurity introduction, while the upper recessed portion receives the side wall insulating layer. This segmentation achieves channel length stability by protecting the critical gate electrode region, while adding minimal structural complexity since the insulating layer is applied only to a specific portion rather than the entire device structure.
Solution Approach 2:
The side wall insulating layer is applied with local quality - only to the recessed portion where it is most needed for channel length control. This localized approach stabilizes the channel length by preventing impurity encroachment near the gate electrode, while minimizing the increase in device complexity by avoiding unnecessary insulating layers in other regions where they would not provide benefit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively stabilizes the channel length and electrical characteristics, improving yield by reducing leakage current and threshold voltage fluctuations, ensuring consistent performance across semiconductor devices.
Implementation Method 1
a side wall insulating layer covering the side wall of the trench in a recessed portion defined by the side wall of the trench and the upper surface of the gate electrode
Implementation Method 2
forming a first conductivity type region along the side wall of the trench in a surface layer portion of the second conductivity type region by introducing a first conductivity type impurity into the surface layer portion of the second conductivity type region via the side wall insulating layer
Data Source
AI summary
A semiconductor device includes a semiconductor layer of a first conductivity type having a main surface at which a trench is formed, a gate insulating layer formed along a side wall of the trench, a gate electrode embedded in the trench with the gate insulating layer interposed therebetween and having an upper surface located below the main surface of the semiconductor layer, a second conductivity type region formed in a surface layer portion of the main surface of the semiconductor layer and facing the gate electrode with the gate insulating layer interposed therebetween, a first conductivity type region formed in a surface layer portion of the second conductivity type region and facing the gate electrode with the gate insulating layer interposed therebetween, and a side wall insulating layer covering the side wall of the trench in a recessed portion defined by the side wall of the trench and the upper surface of the gate electrode.