Vertical Trench Hardmask and BDI Integration for GAA CMOS
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Solution Overview
Problem
Current CMOS fabrication processes for GAA transistors require frequent deposition and removal of hardmask layers due to limited space between channel pillars, complicating S/D module integration and impacting gate spacer formation.
Innovation Solution
A method involving the deposition of a conformal oxide layer, selective etching, and nitride layer formation in vertical structures to simultaneously form hardmask layers on PFET S/D epi and partial BDI layers at the NFET S/D region, using a multi-chamber cluster tool to maintain a controlled environment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardmask is continuously deposited and removed to form S/D epi layer in vertical trench structures, then source/drain epitaxial growth can be achieved, but the process complexity increases and manufacturing efficiency decreases
Solution Approach 1:
The patent combines the hardmask layer and bottom dielectric isolation (BDI) layer into a single integrated layer structure. The nitride layer serves dual functions: as a hardmask during epi growth and as a BDI layer for electrical isolation, eliminating the need for separate hardmask deposition and removal cycles while maintaining device reliability
Solution Approach 2:
The nitride layer is designed to perform multiple functions simultaneously: it acts as a hardmask to prevent epi growth on NFET channels during PFET S/D formation, serves as a BDI layer for electrical isolation between NFET and PFET, and provides a planarization surface. This multi-functionality reduces process steps and complexity
2Manufacturing precision
If hardmask is removed frequently between epitaxial growth steps, then channel pinching is prevented, but manufacturing time and process steps increase
Solution Approach 1:
By merging the hardmask and BDI layer functions into a single nitride layer that extends across the entire substrate surface, the patent eliminates the need for repeated hardmask removal steps. The integrated layer remains in place throughout the process, preventing channel pinching while maintaining manufacturing efficiency
Solution Approach 2:
The nitride layer is deposited as a continuous layer across the entire substrate before any epi growth occurs, establishing both the hardmask and BDI functions in advance. This preliminary action eliminates the need for intermediate removal and redeposition cycles, improving productivity while maintaining precision
3Area of stationary object
If conformal oxide layer is deposited on all vertical surfaces, then complete coverage is achieved, but selective area etching complexity increases
Solution Approach 1:
The patent uses selective etching processes that target specific regions of the conformal oxide layer based on local requirements. The oxide is removed from NFET contact trenches to expose channels for epi growth, while being retained on PFET contact trenches to protect during epi deposition. This local differentiation is achieved through selective etching chemistry and process parameters
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces the frequency of hardmask removal during CMOS processing, preserving device performance by integrating hardmask and BDI layers efficiently.
Implementation Method 1
depositing a conformal oxide layer on vertical trench surfaces and bottom surfaces of vertical trenches
Implementation Method 2
depositing a conformal oxide layer on vertical trench surfaces and bottom surfaces of vertical trenches
Implementation Method 3
selectively depositing a nitride layer at the bottom surface of the vertical structures
Data Source
AI summary
Embodiments described herein generally relate to methods of forming hardmask and bottom dielectric isolation layers in vertical trench structures. A method of forming a gate-all-around field-effect transistor includes depositing a conformal oxide layer on a channel surface and a bottom surface of vertical structures of a substrate, the vertical structures including an NMOS portion having NMOS vertical structures defining NMOS contact trenches and a PMOS portion having PMOS structures defining PMOS contact trenches having a PMOS source/drain layer deposited therein. The method further includes selectively etching the conformal oxide layer at the bottom surface of the vertical structures, inhibiting the conformal oxide layer, selectively depositing a nitride layer at the bottom surface of the vertical structures, etching the conformal oxide layer to expose the channel surface of the vertical structures, and depositing an NMOS source/drain layer on the bottom surface of the NMOS contact trenches.