Trench Gate IGBT Cell Structure for Short-Circuit and Vcesat Balance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Trench gate IGBTs fail to achieve a balance between saturation current, conduction voltage drop (Vcesat), and short circuit tolerance, leading to compromised performance.
Innovation Solution
A cell structure with multiple trench gates of different configurations, including true and virtual gates, is designed to improve the balance between saturation current, conduction voltage drop, and short circuit tolerance, featuring a substrate with sequentially disposed trench gates, well regions, and source regions, with specific trench gate configurations and interlayer dielectric layers to optimize electrical connections and isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the current density is increased in trench gate IGBT, then the cell size is decreased, but the short circuit time is decreased
Solution Approach 1:
The gate structure is segmented into multiple independent gates (first gate, second gate, third gate) with different configurations. Each gate can be independently controlled and optimized for specific functions, allowing the device to achieve both high current density and adequate short circuit time by distributing current through multiple gate regions rather than increasing density in a single region.
Solution Approach 2:
Different regions of the gate structure are given different properties: the first gate has a specific depth and width configuration optimized for one function, while the second gate has different dimensions optimized for another function. This local differentiation allows each region to contribute differently to overall device performance, balancing cell size reduction with short circuit time maintenance.
2Quantity of substance
If the saturation current is increased, then the conduction voltage drop is decreased, but the short circuit tolerance is decreased
Solution Approach 1:
The current conduction path is segmented across multiple gate regions. The first gate region handles a portion of the saturation current while the second gate region handles another portion, distributing the current load. This segmentation allows the device to achieve high total saturation current while each individual region maintains adequate short circuit tolerance.
Solution Approach 2:
The invention changes the parameters of different gate regions (depth, width, doping concentration) to optimize their respective contributions to saturation current and short circuit tolerance. By adjusting these parameters locally in different gate regions, the device achieves high overall saturation current while maintaining short circuit tolerance through proper parameter distribution.
Data Source
AI summary
Disclosed are a cell structure of a semiconductor device, a preparation method thereof and a semiconductor device. The cell structure includes: a substrate of a first conductive type; at least one first trench gate, at least one second trench gate, at least one third trench gate, and at least one fourth trench gate that are sequentially disposed side by side in an upper surface of the substrate; a source region of the first conductive type located in an upper surface of the well region and disposed on two sides of each trench gate; and an emitter metal layer located above the substrate and electrically connected to the source region, where the first trench gate, the second trench gate, and the third trench gate are isolated from the emitter metal layer by a first interlayer dielectric layer, and the fourth trench gate is electrically connected to the emitter metal layer.