Trench Isolated CMUT Array With Supporting Frame
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Solution Overview
Problem
Existing ultrasonic transducer arrays face challenges in providing connections to each array element, particularly in 2D CMUT arrays, where through-wafer via implementation is limited by difficulties in wafer-to-wafer fusion bonding, and trench isolation requires a carrier wafer that is hard to separate, causing stress and membrane breakage.
Innovation Solution
A trench-isolated CMUT array with a supporting mesh frame built on a silicon-on-insulator (SOI) wafer, using a conductive substrate with trenches for electrical isolation and a mesh structure for mechanical support, eliminating the need for a carrier wafer during deep trench etching and flip-chip bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-wafer via implementation is used for electrical interconnections, then electrical connectivity between front and back sides is achieved, but wafer-to-wafer fusion bonding becomes difficult
Solution Approach 1:
The patent segments the electrical interconnection path into two separate components: through-wafer vias for vertical connectivity and trench isolation structures for lateral separation. This segmentation allows the via structure to provide electrical connectivity while the trench isolation prevents interference with subsequent wafer-to-wafer bonding processes, resolving the contradiction between achieving connectivity and maintaining bonding feasibility.
2Strength
If a carrier wafer is used during deep reactive ion etching and flip-chip bonding, then mechanical support for membranes is provided, but separation of carrier wafer and membrane becomes difficult
Solution Approach 1:
The patent extracts and eliminates the carrier wafer from the processing sequence by implementing trench isolation that provides inherent mechanical support to the membranes during deep reactive ion etching and flip-chip bonding. The trench isolation structure itself serves as the support mechanism, removing the need for a separate carrier wafer and thereby eliminating the separation difficulty that plagues carrier-based approaches.
Solution Approach 2:
The trench isolation structure provides self-service by simultaneously serving multiple functions: electrical isolation between elements, mechanical support for membranes during processing, and structural framework for the array. This self-sufficient design eliminates the need for external carrier wafer support, resolving the contradiction between providing mechanical support and enabling easy separation.
3Strength
If adhesive material is used to attach membrane to carrier wafer, then mechanical support is achieved, but adhesive swelling creates stress that can break membranes
Solution Approach 1:
The patent removes the adhesive material from the system by eliminating the carrier wafer attachment approach. Instead, the trench isolation structure provides mechanical support through its rigid silicon framework, completely avoiding the adhesive material that causes swelling and stress-induced membrane breakage.
4Reliability
If trenches are etched for electrical isolation, then parasitic capacitance is reduced, but mechanical support during etching becomes insufficient
Solution Approach 1:
The patent merges the electrical isolation function and mechanical support function into a single integrated trench isolation structure. The etched trenches provide electrical isolation between array elements while the remaining silicon material forms a rigid mesh framework that provides mechanical support during and after the etching process, resolving the contradiction between achieving electrical isolation and maintaining mechanical support.
Data Source
AI summary
A one or two-dimensional capacitive micro-machined ultrasonic transducer (CMUT) array with supporting frame is provided. The CMUT array has at least three array elements deposited on a conductive substrate. The invention also has at least one CMUT cell in the array element, a conductive top layer deposited to a top side of the element, and a conductive via disposed within the elements. The via is isolated from the conductive top layer and conducts with the substrate. There are at least two isolation trenches in the conductive substrate, and the trenches are disposed between adjacent vias to conductively isolating the vias. A substrate region between the trenches forms a mechanical support frame. At least one conductive electrode is deposited to a bottom surface of the conductive substrate, where the electrode conducts with the via. The support frame eliminates the need for a carrier wafer in the process steps.