Trench-Based MIM Capacitor for High Density ICs
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Solution Overview
Problem
Conventional Metal-Insulator-Metal (MIM) capacitors in IC devices have limitations in achieving high capacitance density and voltage linearity, which are essential for advanced analog circuit applications, particularly as device dimensions scale, leading to increased semiconductor chip area and fabrication costs.
Innovation Solution
The integration of trench-based MIM capacitors with a multi-layer metal stack and dielectric or metal fill materials in a semiconductor substrate, providing additional sidewall capacitance through a trench structure, which increases capacitance per unit area beyond conventional planar capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar MIM capacitor structure is used, then fabrication process is simple, but capacitance density is low and chip area increases
Solution Approach 1:
The patent transitions from a conventional planar (2D) capacitor structure to a trench-based (3D) structure by etching trenches into the substrate and forming capacitor plates on the trench walls and bottom. This dimensional change increases the effective capacitance area without proportionally increasing the chip footprint, thereby achieving higher capacitance density while maintaining fabrication feasibility through standard semiconductor processing techniques.
Solution Approach 2:
The trench-based capacitor structure embeds the capacitor elements within the substrate by forming trenches and filling them with capacitor plates and dielectric materials. This nesting approach allows the capacitor to be integrated within the existing substrate volume rather than occupying additional surface area, effectively increasing capacitance density without proportionally increasing chip area.
2Productivity
If device dimensions are scaled down, then circuit density increases, but capacitance density must increase to maintain performance
Solution Approach 1:
By implementing the capacitor in a trench-based 3D structure rather than a planar configuration, the effective capacitance area is increased through the trench walls and bottom surfaces. This allows capacitance density to scale effectively as device dimensions are reduced, maintaining the required capacitance performance while enabling higher circuit density through continued miniaturization.
3Measurement precision
If precision capacitors with high voltage linearity are used, then voltage linearity improves, but capacitance density decreases
Solution Approach 1:
The patent achieves high voltage linearity (less than ±1 ppm) while maintaining high capacitance density (larger than 1 fF/μm²) by carefully selecting and optimizing the dielectric material properties and capacitor plate configuration in the trench structure. The dielectric layer is engineered to provide both the required voltage linearity characteristics and high capacitance density, resolving the trade-off between these two parameters.
Data Source
AI summary
An integrated circuit (IC) includes a semiconductor surface layer of a substrate including circuitry formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal (MIM) capacitor. A multi-layer metal stack on the semiconductor surface layer includes a bottom plate contact metal layer including a bottom capacitor plate contact. A first interlevel dielectric (ILD) layer is over the bottom plate contact metal layer. The MIM capacitor includes a trench in the first ILD layer over the bottom capacitor plate contact, wherein the trench is lined by a bottom capacitor plate with a capacitor dielectric layer thereon, and a top capacitor plate on the capacitor dielectric layer. A fill material fills the trench to form a filled trench. A second ILD layer is over the filled trench. A filled via through the second ILD layer provides a connection to the top capacitor plate.