Trench Gate MOSFET Structure for Electric Field Control
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Solution Overview
Problem
Conventional trench structure MOSFETs face issues with electric field concentration at the trench gate edge, leading to reduced reliability and difficulty in precisely controlling the channel area and short circuit characteristics.
Innovation Solution
The power semiconductor device incorporates a substrate with an epi layer, a plurality of wells, a gate, and a gate insulating layer, where the wells are positioned to surround the lower edge region of the trench gate, and the second doped region is formed through an epitaxial re-growth process to control the channel length and prevent electric field concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a trench structure MOSFET is used, then high voltage capability is achieved, but electric field concentration occurs at the trench gate edge
Solution Approach 1:
The patent applies local quality by creating a P-shield region with different doping characteristics at the trench gate edge compared to other areas. This localized doped region modifies the electric field distribution specifically at the problematic edge area, reducing field concentration while maintaining the overall trench structure's high voltage capability.
Solution Approach 2:
The P-shield region acts as an intermediary element between the trench gate and the drift region. This intermediate doped region serves as a buffer that redistributes the electric field, preventing direct concentration at the trench gate edge while allowing the device to maintain its voltage blocking capability.
2Object-affected harmful factors
If P-shield process is performed to solve electric field concentration, then field distribution improves, but process complexity and cell pitch increase
Solution Approach 1:
The patent merges the P-shield region formation with the existing trench fabrication process. The P-shield doping is performed in the same process sequence as the trench formation and other doping steps, combining multiple functions into a unified process flow rather than adding separate dedicated steps.
Solution Approach 2:
The P-shield region serves multiple functions simultaneously: it reduces electric field concentration at the trench gate edge, provides additional voltage blocking capability, and helps define the cell structure. This multi-functionality reduces the need for separate dedicated structures or processes.
3Ease of manufacture
If conventional trench structure is used, then manufacturing is simplified, but channel area control precision is reduced
Solution Approach 1:
The patent applies preliminary action by forming the P-shield region before finalizing the gate structure. This pre-formed doped region provides a defined boundary that guides subsequent processing steps, enabling more precise control of the channel area while maintaining relatively simple manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively prevents electric field concentration, allows precise control of the channel length, enhances the reliability of the device during high-speed switching, and reduces the risk of damage during the doping region formation.
Implementation Method 1
a gate insulating layer (155) disposed to surround at least a portion of the gate (160)
Implementation Method 2
a doped region of a first conductivity type (140) disposed on a side of the gate insulating layer (155)
Data Source
AI summary
A power semiconductor device includes a substrate; an epi layer of a first conductivity type disposed on the substrate; a plurality of wells of the second conductivity types disposed spaced apart from each other on the epi layer; and a gate disposed between the wells and a gate insulating layer disposed to surround the gate; and a doped region of the first conductivity type disposed on a side of the gate insulating layer. The doped region may include a first doped region of the first conductivity type having a first horizontal width and a second doped region of the first conductivity type disposed below the first doped region and having a second horizontal width smaller than the first horizontal width.


