Trench Non-Volatile Memory Cell with Charge Trapping Layer
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Solution Overview
Problem
Existing split gate non-volatile memory cells with a trapping charge layer are too large for effective storage, limiting their size and efficiency.
Innovation Solution
A non-volatile memory cell design featuring a substrate with a trench, where a charge trapping layer is positioned adjacent to a channel region with a conductive gate, and a control gate is disposed over another portion of the channel region, allowing for capacitive coupling and efficient charge control, reducing the overall size while maintaining functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a split gate non-volatile memory cell with a trapping charge layer is designed, then charge storage functionality is achieved, but the cell size becomes too large
Solution Approach 1:
The patent transitions from a planar memory cell layout to a three-dimensional structure by forming the charge trapping layer within a trench that extends vertically into the substrate. This vertical dimension allows the charge storage function to be achieved without increasing the lateral footprint of the memory cell, effectively resolving the contradiction between functionality and size.
Solution Approach 2:
The patent nests multiple functional components within the trench structure: the charge trapping layer is positioned within the trench, the first gate is formed over the trench, and the second gate is positioned adjacent to the trapping layer. This nested arrangement consolidates multiple functions into a compact vertical stack, reducing the overall cell area while maintaining charge storage capability.
2Area of stationary object
If the memory cell size is reduced, then storage density increases, but charge control precision may be compromised
Solution Approach 1:
The patent implements local quality by creating distinct regions with different doping types (first doped region and second doped region with opposite polarity) and positioning gates at specific locations within the trench. This localized structuring ensures precise electric field control and charge confinement in each region, maintaining charge control precision even as the overall cell size is reduced.
Solution Approach 2:
The patent segments the channel region into two distinct portions: a first channel portion adjacent to the trapping layer controlled by the first gate, and a second channel portion controlled by the second gate. This segmentation allows independent control of charge injection and readout operations, preserving operational precision in the compact structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a smaller size for the memory cell while maintaining operational efficiency through capacitive coupling and precise control of charge conduction, enhancing storage capabilities.
Implementation Method 1
An electrically conductive gate is in the trench, adjacent to and insulated from the charge trapping layer and from the first region and is capacitively coupled to the charge trapping layer
Data Source
Figure 1~2A
Figure 2B~2C
Figure 2D~2E
AI summary
A memory cell comprises a trench in the surface of a substrate. First and second spaced apart regions (14, 16) are formed in the substrate with a channel region therebetween. The first region (14) is formed under the trench. The channel region includes a first portion (18b) that extends along a sidewall of the trench and a second portion (18a) that extends along the surface of the substrate. A charge trapping layer (22) in the trench is adjacent to and insulated from the first portion of the channel region for controlling the conduction of the channel region first portion. An electrically conductive gate (20) in the trench is adjacent to and insulated from the charge trapping layer and from the first region and is capacitively coupled to the charge trapping layer. An electrically conductive control gate (24) is disposed over and insulated from the second portion of the channel region for controlling its conduction.