Trench Polysilicon ESD Diodes for Power MOSFET Gate Protection
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Solution Overview
Problem
Conventional ESD protection circuits for power transistors require significant substrate area and increased step height to achieve higher ESD ratings, limiting their effectiveness and increasing costs, while also complicating advanced photolithography processes.
Innovation Solution
The implementation of back-to-back pn junction diodes formed in a trench polysilicon layer within the semiconductor substrate, where the polysilicon layer extends above the substrate surface, allowing for increased cross-sectional area without substantial substrate real estate or step height, decoupling ESD diode fabrication from power transistor fabrication and enabling advanced lithography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection circuits use larger substrate area to increase diode cross-sectional area, then ESD protection rating is improved, but substrate real estate is consumed and step height increases
Solution Approach 1:
The patent transitions from planar diode structures to three-dimensional vertical structures by forming diodes in trenches that extend through the substrate thickness. This vertical dimensionality change allows increased cross-sectional area for ESD protection without consuming additional substrate footprint area, resolving the contradiction between ESD rating improvement and substrate area consumption.
2Reliability
If conventional ESD protection circuits increase substrate area, then ESD protection rating is improved, but manufacturing cost increases
Solution Approach 1:
By utilizing the vertical dimension through trench formation and extending diode structures through substrate thickness, the patent achieves higher ESD protection ratings without requiring larger substrate areas. This maintains manufacturing cost efficiency while improving reliability, as the same substrate real estate delivers enhanced protection capability.
3Reliability
If conventional ESD protection circuits increase substrate area, then ESD protection rating is improved, but photolithography process complexity increases
Solution Approach 1:
The trench-based vertical diode structure simplifies photolithography processes by eliminating the need for complex multi-layer planar patterning required for large-area conventional diodes. The vertical configuration allows for more straightforward alignment and fabrication steps, reducing process complexity while achieving superior ESD protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances ESD protection ratings by increasing the cross-sectional area of the diodes while minimizing substrate usage and step height, thus improving the ESD protection without increasing costs or complicating the fabrication process.
Implementation Method 1
the breakdown voltage of diodes D1 and D2 are greater than the maximum operating voltage at the gate terminal but less than the gate dielectric breakdown voltage. In this manner, power MOSFET 1 operates normally within the operating voltage range but the diode strings of D1 and D2 are activated in case of a high voltage ESD event to divert away current to protect the gate terminal
Data Source
AI summary
A protection structure for a power transistor includes one or more pairs of back-to-back pn junction diodes formed in a trench polysilicon layer provided in trenches formed in a semiconductor substrate. At least a portion of the trench polysilicon layer protrudes above the top surface of the semiconductor substrate. Alternating N-type doped regions and P-type doped regions are formed in the trench polysilicon layer along a length of the trench. The protection structure, when coupled across the gate and source terminals of the power transistor can be advantageously applied to protect the power transistor from high voltage ESD events.