Vertical Trench-Stacked Decoupling Capacitor for High Capacitance Density
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Solution Overview
Problem
There is a need to miniaturize and increase the capacitance of decoupling capacitors to support the multifunctionality of electrical devices, as insufficient capacitance can lead to operational issues or failure.
Innovation Solution
A semiconductor structure is fabricated by forming a trench capacitor and a stacked capacitor in parallel, with conductive and dielectric structures aligned vertically within a substrate, and connected through electrode plates, allowing for high capacitance in a compact volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional decoupling capacitor structures are used, then the capacitor can be manufactured with conventional processes, but the capacitance per unit volume is insufficient
Solution Approach 1:
The patent implements a nested capacitor structure where a first capacitor is formed within a trench and a second capacitor is stacked above it, with the second capacitor nested over the first capacitor structure. This nesting arrangement allows two capacitive elements to occupy a vertically stacked space, effectively doubling the capacitance within a compact volume without requiring lateral expansion.
Solution Approach 2:
The patent transitions from planar capacitor layouts to a three-dimensional stacked configuration. By forming capacitors in vertical layers with electrode plates at different heights and connecting them through conductive vias, the design exploits the vertical dimension to increase capacitance density. This dimensional change allows multiple capacitive elements to be integrated within a small footprint area.
2Volume of moving object
If capacitor size is reduced to miniaturize the decoupling capacitor, then volume occupancy decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the capacitor structure into distinct segments: a first capacitor in the trench, a second capacitor stacked above, electrode plates, and conductive vias. Each segment is formed through separate manufacturing steps with defined geometric parameters. This segmentation allows independent optimization and control of each component's dimensions and positions, making the overall miniaturization process more manageable and precise.
Solution Approach 2:
The patent employs specific parameter specifications to control manufacturing precision, including substrate thickness of 5-10 micrometers, trench depth of 1-3 micrometers, and controlled fill ratios for conductive structures. By defining and controlling these critical parameters, the patent achieves miniaturization while maintaining manufacturability through standardized process parameters.
Data Source
AI summary
A semiconductor structure includes a trench capacitor, a stacked capacitor, a first electrode plate, and a second electrode plate. The trench capacitor is located in a substrate, in which the trench capacitor has a first conductive structure and a first dielectric structure in contact with the first conductive structure. The stacked capacitor has a second conductive structure and a second dielectric structure in contact with the second conductive structure, in which the stacked capacitor is at least partially aligned with the trench capacitor in an axis vertical to a top surface of the substrate, and the first and second conductive structures are electrically connected. The trench capacitor and the stacked capacitor are electrically connected in parallel between the first and second electrode plates.