Insulating Trench TRIAC Structure for Noise-Immune Triggering

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Solution Overview

Problem

TRIACs are sensitive to noise, leading to mis-triggering and circuit malfunctions due to their susceptibility to small current fluctuations, which affects their reliability in controlling alternating current.

Innovation Solution

A trench is introduced in the semiconductor design, bisecting the N+ regions, P regions, and N- region, creating two operational halves that improve noise immunity and performance by eliminating shunt current and enhancing static dv/dt and commutating performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a traditional TRIAC structure is used, then the device can control alternating current in both directions, but the device is highly sensitive to noise causing mis-triggering

Engineering Contradiction:
Improvenoise immunityVSAvoidnoise sensitivity
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The gate terminal is divided into two separate gate terminals (G1 and G2), each controlling one of the two thyristors. The insulating trench physically separates the two thyristor structures, isolating their respective gate regions. This segmentation prevents noise from affecting both thyristors simultaneously and allows independent gate control, thereby improving noise immunity while maintaining bidirectional current control capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

An insulating trench is introduced as an intermediary element between the two thyristor structures. This trench, filled with insulating material, acts as a barrier that blocks noise coupling between the thyristors while maintaining electrical isolation. The intermediary structure enables the device to achieve high noise immunity without sacrificing the bidirectional switching function.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If the gate terminal is made very sensitive to activate the device, then the device can be easily triggered, but the device becomes susceptible to noise causing mis-triggering

Engineering Contradiction:
Improvegate activation sensitivityVSAvoidmis-triggering resistance
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The single gate terminal is segmented into two independent gate terminals (G1 and G2), each associated with a separate thyristor structure. This segmentation allows each gate to be optimized for its specific thyristor, maintaining high sensitivity for intended triggering while the physical separation through the insulating trench prevents noise from causing unintended triggering of either thyristor.

Inventive Principle:
Principle #1Segmentation

3Reliability

If a trench is introduced to improve noise immunity, then noise sensitivity is reduced, but the device complexity increases

Engineering Contradiction:
Improvenoise immunityVSAvoidstructural complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The insulating trench is introduced by removing material from the semiconductor substrate, extracting a portion of the continuous structure to create isolated regions. This extraction approach achieves noise immunity by physically separating the thyristor structures while maintaining a relatively simple overall device architecture, as the trench formation is a straightforward fabrication process.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentEP4398309A1High noise immunity triac structure with insulating trench
Publication Date: 2024.07.10 LITTELFUSE SEMICON WUXI
  • EP4398309A1 patent drawingFigure 1A~1B
  • EP4398309A1 patent drawingFigure 1C~1D
  • EP4398309A1 patent drawingFigure 2A

AI summary

A TRIAC semiconductor includes an N- region (310), multiple N+ regions (314a-e), and a trench (326). The N- region (310) is sandwiched between two P regions (308, 312). The first P region (308) is connected to an MT2 terminal and the second P region (312) is connected to two MT1 terminals. The multiple N+ regions are located within the first P region (312). The trench (326) is located between two gate terminals (G).