Trenched Storage Elements for Flash Memory Cells
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Solution Overview
Problem
Conventional dual bit memory cells face issues with program disturb and short channel effects due to decreasing process geometries, leading to contamination of one bit by its neighboring bit and inefficient erase mechanisms, which degrade reliability.
Innovation Solution
The implementation of dual storage node memory cells with physically separated storage nodes in trenches, using insulators to prevent charge contamination and allowing for a longer channel length, improved programming efficiency, and efficient charge removal through the use of silicon rich nitride or polysilicon as the charge storage layer, enabling the use of a thinner gate oxide.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If process geometry is decreased to increase memory density, then memory capacity is improved, but program disturb increases causing bit contamination
Solution Approach 1:
The continuous charge trapping layer is divided into separate charge trapping regions that are physically isolated from each other. Each region is associated with a specific bit and is separated by regions without charge trapping layers, preventing charge migration between adjacent bits even when process geometry is reduced.
Solution Approach 2:
The charge trapping layer is removed from specific regions between the source/drain structures to create isolated charge trapping zones. This extraction of the charge trapping layer from continuous form prevents charge contamination while maintaining the necessary charge storage capability for each bit.
2Quantity of substance
If channel length is reduced to increase memory density, then memory capacity is improved, but short channel effects worsen
Solution Approach 1:
The charge trapping layer is positioned in a vertical dimension above the channel rather than extending horizontally. This dimensional change allows the channel length to be reduced for higher density while the vertical charge trapping structure maintains effective gate control and reduces short channel effects.
3Ease of manufacture
If continuous charge trapping layer is used, then manufacturing is simplified, but charge contamination between bits occurs
Solution Approach 1:
The charge trapping layer is segmented into discrete regions using selective removal processes. Regions without charge trapping layers are created between adjacent bits by removing the layer from areas above the channel, while preserving it above the source/drain structures where charge storage is needed.
4Ease of operation
If hot hole injection is used for erase, then erase capability is achieved, but interface damage occurs degrading reliability
Solution Approach 1:
The charge trapping layer is removed from regions above the channel where hot hole bombardment would cause damage. This creates a protective structure where the charge trapping layer exists only above source/drain regions, eliminating the harmful interface states while preserving erase capability through charge removal from the preserved regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces program disturb, enhances programming speed, improves erase reliability, and mitigates short channel effects, resulting in more reliable and efficient memory cell performance.
Implementation Method 1
Programming of a dual bit memory cell 100 can be accomplished, for example, by hot electron injection. Hot electron injection involves applying appropriate voltage potentials to the gate, source, and drain of the cell 100 for a specified duration until the charge trapping layer 140 accumulates charge.
Implementation Method 2
FIG. 1A illustrates a conventional dual-bit memory cell 100. Conventional dual bit memory cell 100 typically includes a substrate 110 with source/drain regions 120 implanted therein, a first oxide layer 130 above the substrate 110, a continuous charge trapping layer 140, a second oxide layer 150, and a poly layer 160.
Implementation Method 3
Erasure of a dual bit memory cell can be accomplished using, for example, the conventional technique of 'hot hole injection' (sometimes referred to as band-to-band (BTB) hot hole injection). In hot hole injection, appropriate voltages are applied to the gate and a drain, while the source is floated or grounded, to erase one of the memory cells
Implementation Method 4
The generated holes are accelerated in the electrical field created near the P-N drain/body junction.
Data Source
AI summary
An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench. The first trench and the second trench each define a first side wall and a second sidewall respectively. The memory cell further includes a first storage element formed on the first sidewall of the first trench and a second storage element formed on the second sidewall of the second trench.