Tri-Gate FeFET Structure With Gate-Last Threshold Voltage Stability
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Solution Overview
Problem
Existing semiconductor manufacturing processes for ferroelectric field effect transistors (FeFETs) face challenges such as low contact area between source/drain metal and oxide semiconductor channel, low effective channel width, and negative impacts on threshold voltage due to thermal processes after gate formation.
Innovation Solution
A gate-last process is employed in forming FeFETs, along with a tri-gate structure and a semiconductor layer that wraps around the source/drain metal electrodes, increasing the contact area and effective channel width, and reducing thermal impacts on threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate formation is performed before source/drain metal deposition, then the manufacturing process follows conventional sequencing, but thermal processes after gate formation negatively impact threshold voltage
Solution Approach 1:
The patent inverts the conventional gate-first sequence by implementing a gate-last process where source/drain metal electrodes are deposited and patterned before forming the gate electrode. This reversal eliminates subsequent thermal processes that would expose the gate to damaging heat, thereby stabilizing threshold voltage while maintaining manufacturing feasibility through adjusted process sequencing
2Device complexity
If conventional planar structure is used, then fabrication is simpler, but contact area between source/drain metal and oxide semiconductor channel is low
Solution Approach 1:
The patent transitions from a two-dimensional planar contact interface to a three-dimensional wrap-around contact structure where the oxide semiconductor layer envelops the source/drain metal electrodes. This dimensional change increases the contact area between metal and channel while maintaining fabrication simplicity through conformal deposition techniques
3Ease of manufacture
If conventional gate structure is used, then manufacturing is easier, but effective channel width is low
Solution Approach 1:
The patent extends the channel structure from a planar surface into the third dimension by having the oxide semiconductor layer wrap around the source/drain metal electrodes. This creates additional channel pathways along the sidewalls, effectively increasing the channel width without complicating the manufacturing process
4Reliability
If source/drain metal electrodes are deposited before oxide semiconductor layer, then gate-last process is enabled, but process sequencing becomes more complex
Solution Approach 1:
The patent performs preliminary deposition and patterning of source/drain metal electrodes before forming the oxide semiconductor layer and gate structure. This preliminary action establishes the metal framework early in the process, enabling subsequent conformal deposition steps and simplifying the overall gate-last sequencing despite the reversed order
Data Source
AI summary
A semiconductor structure includes an isolation layer; first and second source/drain (S/D) metal electrodes over the isolation layer; a metal gate disposed laterally between the first and the second S/D metal electrodes; a ferroelectric layer on a bottom surface and sidewall surfaces of the metal gate; and an oxide semiconductor layer. The oxide semiconductor layer includes a first portion under the first and the second S/D metal electrodes; a second portion under the ferroelectric layer and being thicker than the first portion; third portions above the first and the second S/D metal electrodes, respectively; and fourth portions on sidewalls of the first and the second S/D metal electrodes, respectively, and connecting the third portions to the second portion.