Tri-Layered Gate Stack Reducing Subthreshold Swing in Semiconductors
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Solution Overview
Problem
Semiconductor devices face challenges with increasing feature sizes, such as noticeable current leakage and power consumption due to the physical limit of subthreshold swing in MOS FET devices, which cannot be reduced below 60 mV/dec.
Innovation Solution
A tri-layered gate-control stack is introduced, comprising a ferroelectric (FE) layer, an anti-ferroelectric (AFE) layer, and a mid-gap metal layer, where the mid-gap metal layer is sandwiched between the FE and AFE layers, enhancing and homogenizing electric fields to render a negative capacitance effect, replacing conventional high-k gate dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional high-k gate dielectric layer is used, then device structure is simple, but subthreshold swing cannot be reduced below 60 mV/dec due to physical limit
Solution Approach 1:
The gate dielectric layer is segmented into three distinct sub-layers: a first sub-layer with higher dielectric constant, a second sub-layer with intermediate dielectric constant, and a third sub-layer with lower dielectric constant. This segmentation allows each layer to contribute differently to the electric field distribution, enabling subthreshold swing reduction below the conventional 60 mV/dec limit while managing the complexity through a systematic multi-layer architecture.
2Reliability
If tri-layered gate-control stack with FE, AFE, and mid-gap metal layers is introduced, then subthreshold swing is reduced to 10 mV/dec, but device complexity increases
Solution Approach 1:
The gate-control stack employs composite material structure combining ferroelectric (FE) material, anti-ferroelectric (AFE) material, and mid-gap metal layer. This composite approach leverages the unique properties of each material: FE provides high dielectric constant and switchable polarization, AFE provides stable non-polarized state and hysteresis control, and mid-gap metal provides field homogenization. The combination achieves superior subthreshold swing control (10 mV/dec) by creating synergistic effects that neither material could achieve alone.
Solution Approach 2:
The mid-gap metal layer acts as an intermediary between the FE and AFE layers, serving multiple functions: it homogenizes the electric field distribution, provides a transition zone for field management, and enables the FE and AFE layers to work together more effectively. This intermediary layer is crucial for achieving the desired subthreshold swing reduction while maintaining device reliability.
3Productivity
If feature size is decreased to increase device density, then more devices per unit area are achieved, but current leakage and power consumption increase
Solution Approach 1:
The invention changes the electrical parameters of the gate dielectric system by introducing a tri-layered structure with different dielectric constants. This parameter change creates a tailored electric field distribution that enhances gate control over the channel, thereby reducing off-state leakage current. The ability to independently tune each layer's thickness and dielectric constant provides additional degrees of freedom for optimizing both device density and power consumption characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces the subthreshold swing from 60 mV/dec to 10 mV/dec, minimizing leakage current and power consumption beyond the physical limits of conventional devices.
Implementation Method 1
The FE layer is provided to enhance electric fields created by the electrode layer and the mid-gap metal layer
Implementation Method 2
the AFE layer is provided to render negative capacitance effect
Implementation Method 3
the mid-gap metal layer is provided to homogenize the enhanced electric fields
Data Source
AI summary
A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack includes a ferroelectric layer disposed on the substrate, a mid-gap metal layer sandwiched between the ferroelectric layer and the substrate, and an anti-ferroelectric layer. The anti-ferroelectric layer is sandwiched between the substrate and the mid-gap metal layer. Alternatively, the ferroelectric layer and the mid-gap metal layer are sandwiched between the anti-ferroelectric layer and the substrate.