Trigger-and-Capture Circuit for Debugging Signal States

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Solution Overview

Problem

Current in-circuit debugging methods, such as using programmable logic devices with trigger-and-capture circuits, face challenges in efficiently managing and storing large volumes of data signals for debugging, particularly in reducing data bandwidth and effectively capturing and displaying signal states when trigger conditions are met.

Innovation Solution

A system incorporating a trigger-and-capture circuit, data compressor, DMA controller, and memory controller is used to compress and store signal data in a memory IC die, allowing for selective data output and efficient storage of compressed data subsets based on trigger conditions, with incremental occurrence counts and run-length encoding for loss-less compression.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If signal states are continuously logged into on-chip memory, then debugging capability is improved, but data bandwidth and storage requirements increase

Engineering Contradiction:
Improvedebugging capabilityVSAvoiddata volume
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts only the necessary data for debugging by using trigger signals to selectively capture signal states only when specific conditions are met, rather than continuously logging all signal states. This extraction approach reduces the quantity of data while maintaining debugging capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the data collection process into discrete trigger-based captures rather than continuous streaming. By dividing the continuous signal monitoring into segmented trigger events, the system reduces overall data volume while preserving important debugging information at each trigger point.

Inventive Principle:
Principle #1Segmentation

2Reliability

If all signal states are captured and stored, then complete debugging information is obtained, but data management complexity increases

Engineering Contradiction:
Improvedebugging information completenessVSAvoiddata management complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system extracts and stores only the signal states relevant to trigger events, eliminating unnecessary data management complexity while maintaining complete debugging information for the critical events that matter.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The trigger condition is defined in advance, allowing the system to prepare and structure data collection in advance. This preliminary configuration simplifies data management by pre-determining what data needs to be captured and how it should be organized.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If trigger conditions are monitored continuously, then accurate signal state capture is achieved, but processing time and resources increase

Engineering Contradiction:
Improvesignal state capture accuracyVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

Instead of continuous processing, the system uses periodic trigger-based sampling. The trigger condition is evaluated continuously, but data capture occurs only at discrete trigger moments, reducing processing time and resources while maintaining accurate signal state capture at the critical events.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS8983790B1Method and system for gathering signal states for debugging a circuit
Publication Date: 2015.03.17 XILINX INC
  • US8983790B1 patent drawing
  • US8983790B1 patent drawing
  • US8983790B1 patent drawing

AI summary

Systems and methods gather data for debugging a circuit-under-test. The system includes a trigger-and-capture circuit, a data compressor, a direct memory access controller, and a memory controller. The trigger-and-capture circuit is coupled to the circuit-under-test for receiving signals from the circuit-under-test. The trigger-and-capture circuit is configured to assert a trigger signal when the signals match a trigger condition. The data compressor is configured to loss-lessly compress the signals into compressed data. The direct memory access controller is configured to generate write and read requests. The write requests write the compressed data to a memory integrated circuit die, and the read requests read the compressed data from the memory integrated circuit die. The memory controller is configured to perform the write and read requests.