Triple-Gate Memory Cell for Independent Bit Storage-Computation
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Solution Overview
Problem
Existing memory technologies cannot perform independent operations on single memory bits, limiting their ability to achieve storage-computation integrated operations.
Innovation Solution
A memory system with memory cells comprising a first gate structure, a second gate structure, and a third gate structure, where the floating gates serve as memory bits and are programmed and erased through FN tunneling by controlling voltages of the control gates and select gates, allowing independent operation of two memory bits within each cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If source-side hot electron injection (SSI) is used for programming, then programming can be achieved with small programming current, but independent operations on single memory bits cannot be achieved
Solution Approach 1:
The memory cell is segmented into two independent memory bits (first memory bit and second memory bit), each with its own floating gate and control mechanism. This segmentation allows independent programming and erasing of each memory bit through selective voltage application to different control gates, resolving the contradiction by enabling bit-level independence while maintaining low current operation
Solution Approach 2:
Different control gates (first control gate and second control gate) are assigned different local functions to selectively program or erase specific memory bits. By applying voltages locally to specific control gates while keeping others at zero voltage, the system achieves local quality control that enables independent operation on single memory bits without increasing overall programming current
2Device complexity
If existing memory structure is used, then simple structure is maintained, but storage-computation integrated operations cannot be achieved
Solution Approach 1:
The memory cell structure is enhanced with multiple control gates that enable the same physical structure to perform multiple functions: storage (through floating gates) and computation (through selective programming/erasing operations). The first and second control gates provide universal control capability that allows the memory cell to function both as storage and as a computational element, achieving storage-computation integration without fundamentally changing the basic memory cell architecture
Solution Approach 2:
The invention adds a control dimension by introducing multiple control gates that can be independently voltage-controlled. This dimensional addition to the control mechanism enables selective operation on different memory bits within the same cell, transforming the structure from simple storage to capable of complex storage-computation operations while maintaining reasonable structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables independent operations on single memory bits and achieves storage-computation integrated operations by allowing selective programming and erasing of memory bits within the memory cells.
Implementation Method 1
Each memory bit comprises a floating gate structure... two stable states are respectively defined as 0 and 1
Implementation Method 2
the two stable states are respectively defined as 0 and 1, and are programmed and erased through FN tunneling
Data Source
AI summary
A memory is disclosed. A memory cell comprises three gate structures sequentially arrayed between a first source-drain region and a second source-drain region. A first gate structure and a third gate structure are formed by superposition of a first gate dielectric layer, a floating gate, a second gate dielectric layer and a polysilicon control gate, so that two memory bits and two control gates are formed. A second gate structure is located between the first gate structure and the third gate structure and serves as a select gate. Erasing and programming operations on the two memory bits formed by the floating gates are realized by FN tunneling. During erasing and programming, the first source-drain region and the second source-drain region are grounded, so that the memory bits can be selected and then erased or programmed only by controlling voltages of the first control gate, the select gate and the second control gate. An operation method of a memory is further disclosed. The two memory bits of the memory cell can be independently operated, so that operations on single memory bits are achieved, and accordingly, storage-computation integrated operations are realized.