Triple-Gate MOS Transistor Layout for Short-Channel Control
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Solution Overview
Problem
Existing triple-gate MOS transistors face challenges in reducing short channel effects and improving performance without increasing manufacturing costs or surface area, while also integrating seamlessly with other electronic components like memory cells.
Innovation Solution
A method for manufacturing a triple-gate MOS transistor involving a semi-conductor substrate with etched trenches for vertical gates and a horizontal gate, using electrically isolating layers and polycrystalline silicon materials, allowing independent control of each gate for enhanced performance and integration with non-volatile memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a continuous gate structure is used to control the channel on all three faces, then channel control is improved, but the transistor cannot be independently controlled and integration with other components is limited
Solution Approach 1:
The continuous gate structure is divided into three separate gates (first vertical gate, second vertical gate, and horizontal gate), each capable of independent control. This segmentation allows different gates to be controlled by different potentials, enabling integration with other electronic components while maintaining effective channel control through coordinated gate operation
2Area of stationary object
If the transistor size is reduced to decrease surface imprint, then manufacturing cost is reduced, but short channel effects increase and channel control deteriorates
Solution Approach 1:
The invention transitions from a planar gate structure to a three-dimensional triple-gate structure that controls the channel from three faces (two vertical faces and one horizontal face). This dimensional change increases the effective gate control area without proportionally increasing the surface footprint, allowing reduced transistor size while maintaining or improving channel control through enhanced electrostatic control from multiple directions
3Reliability
If triple-gate structure is implemented to reduce short channel effects, then channel control is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The manufacturing process merges the formation of the triple-gate structure with standard FinFET fabrication steps. The first and second vertical gates are formed using the same trench etching and filling processes as existing FinFET gates, and the horizontal gate is integrated into the same process flow. This merging approach reduces manufacturing complexity by reusing established process steps rather than introducing entirely new fabrication techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves improved electrical performance with increased current supply and facilitates integration with other electronic devices without significant cost or complexity, maintaining similar performance to existing triple-gate FinFET transistors while allowing for independent gate control and reduced manufacturing costs.
Implementation Method 1
forming an electrically isolating layer on the internal surface of each of said trenches
Implementation Method 2
filling each trench with a semi-conductor or electrically conductor material up to an upper surface of the active region, so as to form a respective vertical gate
Data Source
AI summary
A triple-gate MOS transistor is manufactured in a semiconductor substrate including at least one active region laterally surrounded by electrically isolating regions. Trenches are etched on either side of an area of the active region configured to form a channel for the transistor. An electrically isolating layer is deposited on an internal surface of each of the trenches. Each of the trenches is then filled with a semiconductive or electrically conductive material up to an upper surface of the active region so as to form respective vertical gates on opposite sides of the channel. An electrically isolating layer is then deposited on the upper surface of the area of the active region at the channel of the transistor. At least one semiconductive or electrically conductive material then deposited on the electrically isolating layer formed at the upper surface of the active region to form a horizontal gate of the transistor.