Triple Patterning IC Design Method for High Aspect Ratio Trenches
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In advanced semiconductor technologies, maintaining a desired critical dimension (CD) for patterned photoresist layers with high aspect ratios is challenging due to difficulties in shrinking minimum area and maintaining sharp trench ends, which affects metal fill processes and IC design and fabrication.
Innovation Solution
A method involving the generation of three photomask layouts - one for simple features, one for modified complex features, and one for trimming features - to effectively pattern a material layer using lithography and etching processes, ensuring compliance with design rules and improving trench end resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional single patterning is used, then the fabrication process is simple, but the critical dimension control deteriorates for high aspect ratio photoresist layers
Solution Approach 1:
The patent divides the patterning process into three separate lithography steps (triple patterning) instead of one, where each step creates a portion of the final pattern. This segmentation allows each individual patterning step to work within acceptable aspect ratio limits while achieving the overall small feature size goal that would be impossible with single patterning
Solution Approach 2:
The patent introduces an additional dimensional aspect by using multiple lithography layers (first, second, and third photoresist layers) stacked sequentially. Each layer contributes to the final three-dimensional pattern structure, allowing complex high-aspect-ratio features to be built up in stages rather than attempting to create them in a single layer
2Area of moving object
If feature size is reduced to maintain minimum area, then the IC design density improves, but the trench end resolution deteriorates
Solution Approach 1:
The patent performs preliminary actions by first forming the first photoresist layer pattern, then using it as a mask to form the second photoresist layer, and finally using that to form the third layer. Each preliminary pattern serves as a foundation for the next, allowing precise control of trench ends to be established early in the process and maintained through subsequent steps
Solution Approach 2:
The patent applies different patterning approaches to different regions of the structure. The vertical sidewalls of high aspect ratio features are formed by the sequential layering process, while the trench end regions are controlled by the specific exposure and development conditions of each individual lithography step, allowing optimized local quality for each feature type
3Device complexity
If conventional patterning is used, then the process complexity is low, but the design rule compliance becomes difficult
Solution Approach 1:
The patent segments the pattern formation into three distinct lithography steps, each with its own photoresist layer and exposure process. This segmentation allows design rules to be applied and verified at each individual step rather than attempting to control all features in a single complex patterning operation
Solution Approach 2:
The patent employs dynamic adjustment of patterning parameters at each lithography step. The exposure conditions, development times, and etch parameters are optimized for each specific layer formation step, allowing the process to adapt to the specific requirements of creating high aspect ratio features with precise dimensional control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively addresses the challenges of maintaining critical dimensions and trench end resolution, enabling precise IC design and fabrication by defining IC features without violating design rules, thus enhancing the fabrication of advanced IC technologies.
Implementation Method 1
patterning a first photoresist layer on the material layer using a first photomask; patterning a second photoresist layer on the material layer using a second photomask and a third photomask
Implementation Method 2
etching the material layer through openings of the first photoresist layer; etching the material layer through openings of the second photoresist layer
Data Source
AI summary
The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of IC features. The method includes identifying, from the IC design layout, simple features as a first layout wherein the first layout does not violate design rules; and complex features as a second layout wherein the second layout violates the design rules. The method further includes generating a third layout and a fourth layout from the second layout wherein the third layout includes the complex features and connecting features to meet the design rules and the fourth layout includes trimming features.