Triple-Voting Flop Scan Control for 100% At-Speed Coverage
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Solution Overview
Problem
Conventional triple-voting flops suffer from incomplete at-speed scan coverage due to issues with launch-on-capture testing and launch-on-shift testing, particularly with undetectable slow-to-rise and slow-to-fall faults, and the challenge of routing the scan-enable signal at-speed.
Innovation Solution
An integrated circuit design incorporating a control circuit with OR gates and flip-flops to selectively control the scan enable signals of triple-voting flops, enabling launch-on-control testing that achieves complete at-speed scan coverage without additional physical design constraints or area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If launch-on-capture testing is used for triple-voting flops, then test coverage is improved, but slow-to-rise and slow-to-fall faults remain undetectable
Solution Approach 1:
The patent segments the scan enable signal control into separate control paths for different flip-flops within the triple-voting flop structure. By independently controlling scan enable signals for each flip-flop through OR gates and control logic, the testing method can selectively activate specific flip-flops during different phases of the test cycle, enabling detection of slow-to-rise and slow-to-fall faults that were previously undetectable with uniform launch-on-capture testing
Solution Approach 2:
The patent introduces dynamic control of scan enable signals that transitions between different states during the test cycle. The control circuit dynamically adjusts which flip-flops receive scan enable signals based on the test phase, allowing the system to adaptively test for different fault types (slow-to-rise, slow-to-fall) by changing the activation pattern of individual flip-flops
2Ease of manufacture
If launch-on-shift testing is used for triple-voting flops, then scan enable signal routing is simplified, but at-speed testing capability is lost
Solution Approach 1:
The patent introduces control circuits and OR gates as intermediary elements between the scan enable signal source and the flip-flops. These intermediaries selectively gate the scan enable signals to different flip-flops at different times, enabling the system to use slower-routed scan enable signals while still achieving at-speed testing functionality by controlling the timing and distribution of enable signals through the intermediary logic
3Productivity
If conventional triple-voting flop testing is implemented, then functional operation is maintained, but test time increases due to incomplete coverage
Solution Approach 1:
The patent enables continuous effective testing by eliminating incomplete coverage gaps. The enhanced control method ensures that all flip-flops are properly tested for all relevant fault types (slow-to-rise, slow-to-fall, and functional faults) within a unified test sequence, maintaining continuous useful testing action without requiring repeated or extended test cycles
Data Source
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AI summary
According to an embodiment, a method for testing a triple-voting flop (TVF) is provided. The method includes providing (1302, 1304, 1308) a first and a second scan enable signal by a control circuit to, respectively, a first scan flip-flop and a third scan flip-flop of the TVF; receiving (1306) a third scan enable signal at the second scan flip-flop of the TVF; providing (1310) a scan input signal to the first scan flip-flop, the second scan flip-flop, and the third scan flip-flop; controlling (1312) the first scan enable signal, the second scan enable signal, and the third scan enable signal; receiving, (1314) at an output of the TVF, a scan output signal; and determining (1316) whether the TVF suffers from a fault based on the scan output signal and the controlling of the first scan enable signal, the second scan enable signal, and the third scan enable signal.