Triple-Voting Scan Flop Circuit for Full Fault Coverage
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Solution Overview
Problem
Achieving 100% at-speed and stuck-at scan coverage in triple-voting flops during scan testing is challenging, particularly due to masking of faults in logic circuits during launch-on-capture and launch-on-shift testing.
Innovation Solution
A triple-voting flop design with scan flip-flops and additional logic circuits that control scan enable inputs, allowing independent value loading and improved fault detection through launch-on-capture testing, ensuring comprehensive fault coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional scan testing (LOC or LOS) is used on triple-voting flops, then test implementation is simplified, but fault detection coverage is reduced due to masking effects
Solution Approach 1:
The scan path is segmented into multiple independent scan chains, with each chain containing specific flip-flops that can be individually controlled. This segmentation allows different scan enable signals to be applied to different segments, enabling independent testing of each segment and eliminating the masking effect where faults in one flip-flop could hide faults in another.
Solution Approach 2:
The scan enable signals are made dynamic and configurable, allowing the test system to selectively enable or disable scan operations in different segments during different test phases. This dynamic control enables the test architecture to adapt to different testing requirements and achieve complete fault coverage by preventing masking effects through selective scan chain activation.
2Reliability
If multiple scan chains are used to achieve complete fault coverage, then fault detection capability is improved, but circuit complexity increases
Solution Approach 1:
The additional logic circuits serve multiple functions: they generate scan enable signals for multiple scan chains, control the timing of scan operations, and coordinate the independent testing of different flip-flop segments. By making these logic circuits multi-functional, the patent achieves complete fault coverage without proportionally increasing circuit complexity, as the same logic structures perform multiple testing functions.
Data Source
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AI summary
In an embodiment, an integrated circuit (700) includes: a voting circuit (706) including N scan flip-flops (402, 404, 406), where N is an odd number greater than or equal to 3, and where the N scan flip-flops includes a first scan flip-flop (402) and a second scan flip-flop (406), where an output of the first scan flip-flop (402) is coupled to a scan input of the second scan flip-flop (406); a scan chain (720) including the N scan flip-flops (402, 404, 406) of the voting circuit (706), and third (704) and fourth (708) scan flip-flops, the scan chain configured to receive a scan enable signal (scan_en); and a scan enable control circuit (550, 552) configured to control a scan enable input of the first (402) or second (406) scan flip-flops based on the scan enable signal (scan_en) and based on a scan input of the third scan flip-flop (704) or an output of the fourth scan flip-flop (708).