Truncated CSD Array for Rational Multiplication
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Solution Overview
Problem
Existing methods for implementing division operations in integrated circuits are costly and resource-intensive, especially when the divisor is a constant, as they require complex logic and significant silicon area, and truncating infinite arrays for multiplication by a constant rational can be challenging without accurate error compensation.
Innovation Solution
A method for deriving a hardware representation of a fixed logic circuit that performs multiplication by a constant rational p/q, involving the determination of an infinite CSD expansion, forming a truncated summation array, and calculating a corrective constant to ensure accurate rounding, thereby reducing the complexity and area required for the logic circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If an infinite summation array is used for multiplication by a constant rational, then the accuracy of the result is improved, but the device complexity and area increase infinitely
Solution Approach 1:
The patent extracts only the necessary finite portion of the infinite summation array by identifying and discarding columns where all bits are zero or can be safely truncated. This extracts the essential computational elements while removing the infinite complexity, achieving a finite hardware implementation that maintains accuracy for the required precision.
Solution Approach 2:
The patent performs partial action by computing only enough columns of the summation array to achieve the desired precision, rather than computing the complete infinite array. The truncation point is determined by analyzing when additional columns would not contribute to the final result within the required precision, thus performing just sufficient computation without excess.
2Measurement precision
If more columns are retained in the truncated summation array, then the accuracy is improved, but the silicon area and resource usage increase
Solution Approach 1:
The patent changes the parameter of truncation point based on the desired precision requirements. By analyzing the bit patterns in each column and determining where the contribution to the final result becomes negligible, the method dynamically adjusts how many columns to retain, optimizing the balance between accuracy and silicon area for different precision requirements.
3Quantity of substance
If the truncation point is reduced to save area, then the resource usage decreases, but the rounding accuracy deteriorates
Solution Approach 1:
The patent introduces an intermediary analysis step that examines the bit patterns and carry propagation effects at potential truncation points. This intermediary analysis determines the precise point where truncation can occur without affecting rounding accuracy, acting as a mediator between the conflicting requirements of resource reduction and accuracy maintenance.
Solution Approach 2:
The patent performs preliminary analysis of the summation array columns to identify safe truncation points before final implementation. By pre-analyzing which columns can be discarded without affecting the final rounded result, the method prepares the optimal truncation strategy in advance, ensuring both resource efficiency and rounding accuracy are achieved.
Data Source
AI summary
A hardware representation of a fixed logic circuit is derived for performing multiplication of an input x by a constant rational p/q so as to calculate an output y according to a directed rounding or round-to-nearest rounding mode, where p, q are coprime integers, and x is an m-bit input. An infinite CSD expansion of the rational p/q is determined, a truncated summation array of the bits of the CSD expansion of the rational p/q operating on the bits of the input x is formed by discarding at least the kth column of the array below the position of the binary point, where k=└ ln2(mq)┘+1; further truncating the truncated summation array whilst ensuring thatΔhigh-Δlow<1q,where, for all x, Δhigh is the maximum sum of the partial products discarded from the array and Δlow is the minimum sum of the partial products discarded from the array; determining a corrective constant z in dependence on the rounding mode and the set of partial products discarded from the array such that the output y is correct for all x; and generating a hardware representation of a fixed logic circuit implementing the truncated summation array including the corrective constant z.