TSPC Pre-Charge Flip-Flop for Faster Data Input and Lower Setup Time
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Solution Overview
Problem
Existing flip-flops with cross-coupled multiplexer structures face delays and variations in data input, and are costly to manufacture, due to slower data input paths and increased sensitivity to manufacturing variations.
Innovation Solution
A True Single Phase Clock (TSPC) pre-charge based flip-flop design that includes a scan section, a master section, and a slave section, utilizing a TSPC clock signal to enable faster data arrival and pre-charging of nodes to reduce setup time and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a cross-coupled multiplexer structure is used in flip-flops, then data input functionality is achieved, but data input speed decreases and delay increases
Solution Approach 1:
The patent extracts the multiplexer functionality from the critical data input path and places it in the non-critical feedback path. The scan section receives data input directly without passing through a multiplexer, while the multiplexer is used only for selecting between feedback data and scan data in the less time-sensitive output path. This separation removes the multiplexer-induced delay from the critical data input-to-output path.
Solution Approach 2:
The flip-flop is segmented into distinct functional sections: a scan section for direct data input, a master section with feedback logic, and a slave section with multiplexer-based output selection. This segmentation allows the critical data path to be optimized for speed while the feedback and control paths can use more complex logic structures.
2Ease of manufacture
If a cross-coupled multiplexer structure is used in flip-flops, then data input functionality is achieved, but manufacturing cost increases
Solution Approach 1:
The patent removes the multiplexer from the critical data input path, eliminating the source of manufacturing variations in that path. By placing the multiplexer only in the feedback path where timing is less critical, the design reduces sensitivity to manufacturing variations while maintaining full functionality.
3Loss of time
If nodes are pre-charged in the TSPC flip-flop, then setup time is reduced, but power consumption increases
Solution Approach 1:
The pre-charge operation is performed periodically only during the active phase of the clock signal. The TSPC flip-flop uses edge-triggered pre-charging where nodes are pre-charged just before the clock edge arrives, rather than being continuously charged. This periodic pre-charging minimizes power consumption while still achieving the benefit of reduced setup time.
Data Source
AI summary
A True Single Phase Clock (TSPC) pre-charge based flip-flop is provided. The flip-flop includes a scan section, a master section, and a slave section. The scan section receives a scan enable signal, a scan input signal, a clock signal, and feedback data from the master section, and outputs an internal signal to the master section based on the scan enable signal, the scan input signal, the clock signal, and the feedback data. The master section is coupled to the scan section and receives the internal signal and a data input, and outputs a master feedback signal to the slave section based on the internal signal, the data input, and the feedback data. The slave section is coupled to the master section and generates an output by latching the master feedback signal received from the master section according to the clock signal. The clock signal is a True-Single-Phase-Clock (TSPC).