TSPC Retention Flip-Flop for Low Clock Power and Small Area
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Solution Overview
Problem
Conventional flip-flop designs face challenges in reducing clock power consumption while maintaining performance and area efficiency, as they often degrade frequency and increase area due to the removal of single-stacked structures.
Innovation Solution
A True-Single-Phase-Clock (TSPC) data-retention edge-triggered flip-flop design is proposed, which includes an input circuit, a master circuit, a slave circuit with a retention circuit, and an output circuit, utilizing transistors to receive a global power supply when the retention signal is low, allowing the slave circuit to retain states irrespective of the clock input and enabling efficient power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional stacking technique is used to reduce clock power, then power consumption is reduced, but flip-flop performance degrades and area increases
Solution Approach 1:
The flip-flop is divided into two independent circuits: a main flip-flop circuit for normal operation and a retention circuit for data preservation. This segmentation allows the main circuit to be simplified for performance while the retention circuit handles power reduction, resolving the contradiction between performance and power consumption.
Solution Approach 2:
A retention circuit acts as an intermediary between the main flip-flop and the output, preserving data when the main circuit is powered down. This intermediary enables the main circuit to operate with reduced power consumption while maintaining data integrity through the retention circuit.
2Loss of energy
If single-stacked structures are removed to reduce power, then power consumption is reduced, but area increases
Solution Approach 1:
The retention circuit merges multiple functions (data retention, power gating control, and output buffering) into a single integrated structure. This combining of functions reduces the overall area compared to having separate circuits for each function, while still achieving power reduction goals.
3Reliability
If retention circuit is added to maintain data state, then data retention reliability is improved, but device complexity increases
Solution Approach 1:
The retention circuit is designed to perform multiple functions: data retention during power gating, state preservation across clock cycles, and output buffering. This multi-functionality reduces the need for separate dedicated circuits, thereby reducing overall complexity while improving reliability.
Data Source
AI summary
Embodiments herein disclose a flip flop comprising at least one of a slave circuit and a retention circuit receiving an input from a master circuit. The output circuit receives an input (X1) from at least one of the slave circuit and the retention circuit. A first node and a second node in the retention circuit receive a power supply from a global power supply through transistors, when a retention is 0 in the retention circuit, so that the slave circuit retains a current state of the X1 and X2 irrespective of a clock input in the slave circuit, and the output circuit receives the stored state of the retention circuit, when a local power supply is turned ON.