TSV Air-Gap Cavities Reduce RC Delay
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Solution Overview
Problem
Conventional TSV structures face increased RC delay and signal time delay issues due to miniaturization, which affects the vertical electrical interconnection of semiconductor chips.
Innovation Solution
A TSV structure with insulating layers featuring embedded voids is developed, where air-gap cavities are formed on the sidewalls of the via, and a dielectric liner covers these cavities without filling them, creating an air insulating layer that prevents the conductive filler from entering, thereby reducing capacitance and improving RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If TSV diameter and pitch are miniaturized to reduce semiconductor device size, then device miniaturization is achieved, but RC delay and signal time delay increase
Solution Approach 1:
The patent introduces air-gap cavities (voids) within the dielectric liner surrounding the TSV, creating a porous structure that reduces the effective dielectric constant. This porous configuration lowers capacitance between the conductive filler and surrounding structures, thereby reducing RC delay and signal time delay while maintaining miniaturized TSV dimensions
Solution Approach 2:
The patent creates a composite dielectric structure consisting of a dielectric liner material combined with embedded air-gap cavities. This composite configuration provides lower effective permittivity compared to solid dielectric materials, reducing capacitive coupling and RC delay in miniaturized TSV structures
2Productivity
If TSV diameter and pitch are miniaturized to eliminate bonding wires and achieve vertical stacking, then device miniaturization is achieved, but RC delay increases
Solution Approach 1:
The air-gap cavities embedded in the dielectric liner create a porous structure that reduces capacitance, thereby reducing RC delay and energy loss in the vertical interconnection path, enabling efficient vertical stacking of miniaturized devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The TSV structure with embedded voids effectively reduces signal time delay by lowering the Time constant through the creation of a non-solid dielectric layer on the via sidewall, addressing the limitations of conventional TSV structures.
Implementation Method 1
a non-solid dielectric layer is disposed on the sidewall of TSV to improve RC delay of TSV
Data Source
AI summary
Disclosed is a TSV structure having insulating layers with embedded voids, including a chip layer, a dielectric liner and a conductive filler. There is at least a via reentrant from one surface of the semiconductor body of the chip layer. A plurality of air-gap cavities are formed on the sidewall of the via where the cavities have a depth-to-width ratio not less than one. The dielectric liner covers the sidewall of the via without filling into the air-gap cavities. The conductive filler is disposed in the via without filling into the air-gap cavities due to the isolation of the dielectric liner so as to form an air insulating layer with a plurality of enclosed voids embedded between the semiconductor body and the dielectric liner. Accordingly, RC Delay of the TSV structure can be improved.