Through-Silicon Via Air-Gap Etching for Lower Parasitic Capacitance
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Solution Overview
Problem
Existing through-silicon via (TSV) technologies face limitations in reducing parasitic capacitance, which hinders increased speed due to the presence of parasitic capacitance with semiconductor substrates.
Innovation Solution
A semiconductor apparatus and manufacturing method that form a cavity portion around a conductor within a via penetrating a semiconductor layer, utilizing a conductive material with an opening portion to etch and reduce parasitic capacitance, while ensuring electrical insulation and potentially incorporating insulating materials and surrounding trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a through-silicon via (TSV) is formed to extract electrodes from the back side for semiconductor apparatus downsizing, then the device size is reduced, but parasitic capacitance increases which hinders speed increase
Solution Approach 1:
The patent extracts the dielectric material from the side surface of the TSV to create an air gap cavity. This removes the harmful parasitic capacitance source (dielectric material) while preserving the TSV's electrode extraction function for downsizing.
Solution Approach 2:
The patent introduces an air gap cavity (porous structure) around the TSV conductor. Air has negligible dielectric constant compared to solid dielectric materials, thereby reducing parasitic capacitance while maintaining the structural integrity of the TSV.
2Stress or pressure
If an isolation recess portion is formed in the TSV's liner isolation layer to mitigate stress impact, then stress transfer is reduced, but parasitic capacitance reduction is insufficient
Solution Approach 1:
The patent extends the stress mitigation and capacitance reduction from a localized recess portion to a full-length air gap cavity that spans the entire TSV height. This dimensional extension ensures both stress relief and maximum parasitic capacitance reduction.
Solution Approach 2:
The patent segments the dielectric material around the TSV, removing it completely to form an air gap cavity. This segmentation eliminates the continuous dielectric path that causes parasitic capacitance while maintaining stress isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively decreases parasitic capacitance, enabling high-speed operation and allowing for the downsizing of semiconductor devices by reducing stress transfer and dielectric constants on TSV side surfaces.
Implementation Method 1
a step of etching the etching target material with the conductor in contact with an upper surface side material and a lower surface side material of the layer
Data Source
AI summary
Parasitic capacitance in a through-silicon via (TSV) is reduced. A semiconductor apparatus includes a given layer. A via vertically penetrates the given layer. A conductor is in contact with an upper surface side material and a lower surface side material of the vertically penetrated layer. The conductor forms, between the conductor and an inside of the via, a cavity portion that vertically penetrates the layer without being in contact with the inside of the via. At least either the upper surface side material or the lower surface side material of the layer is a conductive material, and at least part of the conductive material includes an opening portion for the cavity portion. This opening portion is used to supply an etchant during etching.