Configurable Logic via TSV and Antifuse Segmentation
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Solution Overview
Problem
The increasing cost of mask sets for semiconductor manufacturing, particularly for custom Integrated Circuits, and the limitations of existing FPGA technologies in terms of flexibility, re-programmability, and silicon area utilization, pose challenges in achieving efficient and cost-effective production of configurable logic devices.
Innovation Solution
The use of re-programmable antifuse technology in conjunction with Through Silicon Via (TSV) to construct configurable logic devices, allowing for the placement of transistors above or below antifuse configurable interconnect circuits, and the integration of thin film transistors for programming circuits to reduce silicon area usage and mask costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If custom mask sets are used for each unique IC design, then manufacturing precision is improved, but mask set cost increases exponentially
Solution Approach 1:
The patent segments the IC fabrication process into two distinct parts: (1) generic layers that are common across multiple products and can be shared using a single mask set, and (2) custom layers that are specific to each product design. This segmentation allows the expensive custom mask-making to be minimized to only the necessary custom portions, while the bulk of the structure uses shared generic masks.
Solution Approach 2:
The patent creates generic layers that serve multiple functions across different custom IC designs. These generic layers include common structures such as isolation layers, well structures, and standard device layers that can be reused for multiple products, reducing the need for unique mask sets for each design.
2Ease of manufacture
If generic layers are reused across custom products, then mask set cost is reduced, but device customization flexibility is limited
Solution Approach 1:
The patent divides the device structure into generic portions that can be reused and custom portions that can be tailored to specific designs. The custom layers are selectively formed only where needed for each specific application, allowing full customization flexibility while maintaining cost efficiency through shared generic layers.
Solution Approach 2:
The patent performs preliminary fabrication of the generic layers first, establishing a common foundation that can be reused. Then, custom layers are added subsequently for each specific design, allowing the customization to be done efficiently on top of the pre-prepared generic structure without requiring complete redesign of the entire device.
3Area of stationary object
If transistors are placed in the same layer as antifuse configurable interconnect circuits, then silicon area utilization is improved, but programming voltage interference occurs
Solution Approach 1:
The patent resolves the conflict by placing transistors and antifuse configurable interconnect circuits in different vertical layers rather than the same layer. This dimensional separation in the vertical direction allows both components to coexist without electrical interference during programming operations, while still achieving high silicon area utilization through efficient 3D stacking.
Data Source
AI summary
A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.