Through Silicon Via Arrays for 3D IC Power Distribution
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Solution Overview
Problem
Three-dimensional integrated circuits (3D ICs) experience high IR drops due to increased electrical resistance from deep through-silicon vias, leading to power consumption issues and reduced performance.
Innovation Solution
Implementing power grid via arrays with through-silicon vias, grid walls along the chip perimeter, via islands between power grid wires, and conductive bonding pads to reduce electrical resistance and provide additional contact area, thereby minimizing IR drops across chip layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If through-silicon vias are made deeper to increase chip density in 3D IC structures, then vertical integration capability is improved, but electrical resistance increases leading to higher IR drops
Solution Approach 1:
The power distribution network is segmented into multiple via arrays distributed across different locations (center, corners, edges) of the chip. Each via array contains multiple through-silicon vias that work in parallel, dividing the current path into multiple shorter segments. This segmentation reduces the effective resistance and mitigates IR drops while maintaining deep via structures for vertical integration.
Solution Approach 2:
Multiple via arrays are combined to form a comprehensive power distribution network. The via arrays at different locations (center, corners, edges) are merged to create redundant current paths and reduce overall resistance. This merging approach allows the system to achieve both deep via integration for high density and low resistance for voltage stability.
2Loss of energy
If via arrays are added to reduce electrical resistance, then power distribution efficiency is improved, but device complexity increases
Solution Approach 1:
The via arrays serve multiple functions simultaneously: they provide electrical connection for power distribution, act as structural support elements, and function as heat dissipation pathways. This multi-functionality reduces the need for separate dedicated structures, thereby limiting the increase in device complexity while achieving reduced power loss through efficient power distribution.
Solution Approach 2:
Via arrays are strategically placed at specific locations (center, corners, edges) where they are most needed based on local current density and voltage drop characteristics. This localized approach ensures that via arrays are added only where necessary to reduce power loss, rather than uniformly across the entire chip, thus minimizing the increase in overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces power consumption and improves device performance by minimizing voltage drops across 3D IC structures, enhancing the reliability and efficiency of power distribution within the circuits.
Implementation Method 1
power grid via arrays with through-silicon vias... to reduce electrical resistance and provide additional contact area, thereby minimizing IR drops across chip layers
Data Source
AI summary
The present disclosure describes a semiconductor structure includes a first chip with a first conductive line and a first conductive island formed on the first conductive line. The first chip also includes a first plurality of vias formed in the first conductive island and electrically coupled to the first conductive line. The semiconductor structure further includes a second chip bonded to the first chip, where the second chip includes a second conductive line and a second conductive island formed on the second conductive line. The second chip also includes a second plurality of vias formed in the second conductive island and electrically coupled to the second conductive line.