3D Integration TSV Back Side Wiring Architecture
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Solution Overview
Problem
Current 3D wafer stacking technologies face challenges in efficiently connecting multiple semiconductor wafers due to limitations in through silicon vias (TSVs) and back side wiring, which affect the integration density and performance of semiconductor devices.
Innovation Solution
The method involves forming intra-wafer TSVs and back side wiring layers on semiconductor wafers, followed by bonding and extending inter-wafer TSVs through the entire thickness of the wafers to establish electrical connections between stacked IC chips, utilizing a combination of small intra-wafer TSVs and larger inter-wafer TSVs for efficient power and signal distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional through silicon vias (TSVs) are used for 3D wafer stacking, then electrical connections between stacked wafers are established, but area penalties on the front side increase and integration density decreases
Solution Approach 1:
The patent moves wiring and TSV connections from the front side to the back side of the wafer, utilizing the unused back side area for interconnect structures. This dimensional relocation allows the front side to be fully dedicated to active circuitry, maximizing integration density while maintaining electrical connection reliability through the back side TSV architecture.
2Power
If larger TSVs are used for inter-wafer connections, then power and signal distribution is improved, but manufacturing complexity and stress on the wafer increase
Solution Approach 1:
The patent divides TSV connections into two segments: intra-wafer TSVs for fine-pitch connections within a wafer and inter-wafer TSVs for coarse-pitch connections between wafers. This segmentation allows each TSV type to be optimized for its specific function, with inter-wafer TSVs providing robust power and signal distribution while intra-wafer TSVs handling dense local interconnects, thereby reducing overall manufacturing complexity.
3Length of stationary object
If more repeaters are added to extend signal run lengths, then signal distribution capability is improved, but device complexity and area consumption increase
Solution Approach 1:
The patent extends signal run lengths by utilizing the back side of the wafer for wiring layers, allowing signals to travel longer distances without requiring additional repeaters. The back side wiring architecture provides extended signal paths that reduce the need for signal regeneration, thereby decreasing device complexity and area consumption associated with repeater circuits.
Data Source
AI summary
The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.