Through-Silicon Via Testing via Backside Scan Chains
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Solution Overview
Problem
The increasing size of integrated circuits (ICs) leads to higher defect rates, affecting yield, and detecting through-silicon via (TSV) failures is challenging due to the complexity of the interposer structure, which complicates testing and increases fabrication costs.
Innovation Solution
A method involving the formation of scan chains using conductive vias and metal layers on a test interposer wafer, allowing for electrical testing of TSVs by connecting them in series to facilitate detection of failures and improve yield assurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If direct testing of finished interposers is performed, then TSV failures can be detected, but the closeness of the topside contacts makes them very difficult to probe
Solution Approach 1:
The patent transitions from direct topside probing to backside probing through TSVs. By accessing the interposer from the opposite side (backside to topside direction), the testing approach circumvents the probing difficulty caused by closely spaced topside contacts while still enabling TSV failure detection
Solution Approach 2:
The patent introduces an intermediary testing structure consisting of test pads and test circuits formed on the backside of the interposer. These intermediaries enable indirect testing of TSVs by providing accessible test points that are electrically connected to the TSVs through the interposer structure, avoiding direct probing of the difficult-to-access topside contacts
2Reliability
If TSV testing is performed after IC chip mounting, then composite IC functionality can be verified, but adding component and fabrication costs is incurred if a composite IC fails due to TSV failure
Solution Approach 1:
The patent performs TSV testing at an intermediate stage during interposer fabrication, before IC chips are mounted. By conducting the testing preliminarily during the manufacturing process rather than after assembly, defective interposers can be identified and discarded early, preventing wasted investment in subsequent chip mounting and assembly operations
Solution Approach 2:
The patent enables rapid TSV testing by implementing scan chains that allow automated sequential testing of multiple TSVs. This approach facilitates quick identification of defective interposers, allowing the manufacturing process to skip further processing of failed units and rush through to the next testable unit, thereby reducing overall fabrication costs
3Reliability
If scan chains are formed to enable electrical testing of TSVs, then TSV failures can be detected early, but additional metal layer processing is required
Solution Approach 1:
The patent merges the TSV test structure with the existing interposer metal interconnect layers. By forming scan chains using the same metal deposition and patterning processes already required for the functional interposer interconnects, the testing capability is integrated into the standard fabrication sequence without requiring entirely separate processing steps
Solution Approach 2:
The patent designs the metal layers to serve dual functions: forming both the functional interconnect structure required for IC operation and the scan chain test structure required for TSV verification. This multi-functionality allows a single set of metal processing steps to accomplish both interposer functionality and testability, minimizing additional processing complexity
Data Source
AI summary
A silicon interposer has a plurality of conductive vias extending from a first side of a silicon substrate to an opposite side of the silicon substrate. A plurality of first side scan chain links are disposed on the first side of the silicon substrate. Each scan chain link electrically connects two conducting vias of the plurality of the conductive vias together. In some cases, a test fixture connects the opposite side of the conductive vias together and continuity or resistance is measured. In other cases, scan chain links are formed on the opposite side of the wafer to form a scan chain, which is electronically tested.