TSV Bonding Layout for High-Density 3D Semiconductor Stacks
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Solution Overview
Problem
The semiconductor industry faces physical limitations in two-dimensional integrated circuit formation due to increasing interconnection lengths and densities, necessitating new mechanisms for forming semiconductor structures.
Innovation Solution
A method involving the formation of through semiconductor vias (TSVs) and bonding conductors in semiconductor dies, followed by stacking these dies to create a die stack with precise bonding interfaces, utilizing various bonding methods and dielectric layers to enhance connectivity and reduce physical constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional integrated circuit formation continues with successive reductions in minimum feature size, then integration density improves, but physical limitations arise from significant gains in interconnection length and density
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical integration by stacking multiple semiconductor dies. This dimensional change allows continued increase in integration density without proportionally increasing interconnection length, as vertical stacking reduces the horizontal distance signals must travel between components.
2Quantity of substance
If the number of semiconductor devices increases in two-dimensional layout, then integration density improves, but the number and length of interconnections between devices increases significantly
Solution Approach 1:
By stacking semiconductor dies vertically, the patent reduces the horizontal interconnection distance required to connect increased numbers of devices. The vertical dimension provides direct access between tiers, simplifying the interconnection architecture compared to sprawling two-dimensional routing.
Solution Approach 2:
The patent divides the integrated circuit into multiple separate semiconductor dies that are stacked and bonded together. Each die can be independently fabricated and optimized, then assembled into a three-dimensional structure with simplified interconnections through bonding interfaces and through-silicon vias.
3Quantity of substance
If existing integrated circuit design rules are used with decreasing pitch for conductive wirings, then integration density improves, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent segments the manufacturing process into separate fabrication stages for individual dies, followed by assembly through bonding. This allows each die to be manufactured using conventional processes without requiring extreme miniaturization, while achieving high overall density through vertical stacking.
Solution Approach 2:
The patent introduces bonding interfaces and through-silicon vias as intermediary structures that connect separate dies. These intermediaries enable high-density integration without requiring the conductive wirings within individual dies to be miniaturized beyond conventional manufacturing capabilities.
Data Source
AI summary
A manufacturing method of a semiconductor structure includes forming a first interconnect structure over a first semiconductor substrate; forming a through substrate via (TSV) to penetrate through the first semiconductor substrate and extend into the first interconnect structure, where the TSV includes a first surface in the first interconnect structure and a second surface opposite to the first surface; and forming a first bonding conductor on the first interconnect structure to be electrically coupled to the TSV through the first interconnect structure, where the first bonding conductor includes a first bonding surface facing away the first interconnect structure, and a boundary of the first bonding surface of the first bonding conductor overlaps a boundary of the first surface of the TSV.