Through-Substrate Via Chip Guard Ring for Grounding
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Solution Overview
Problem
The design of compact high-performance semiconductor chips is challenging due to the need for adequate grounding, which requires multiple grounding pads to block spurious signals and stabilize voltage, but increasing the number of pads increases chip size and bonding costs, while reducing them degrades circuit performance.
Innovation Solution
The implementation of through-substrate vias and a metallic enclosure structure around the semiconductor chip, which functions as an electrical ground without the need for grounding metal pads, reducing inductance and enhancing signal isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple grounding metal pads are used on the guard ring, then grounding performance and spurious signal blocking are improved, but chip size and bonding costs increase
Solution Approach 1:
The invention transitions from planar grounding pads on the chip surface to three-dimensional through-substrate vias that extend vertically through the entire chip thickness. This dimensional change allows grounding connections to be made at both the top and bottom surfaces of the chip, effectively utilizing the vertical dimension to achieve adequate grounding without increasing the horizontal chip area.
Solution Approach 2:
The through-substrate via structure serves multiple functions simultaneously: it provides electrical grounding, acts as a shield against spurious signals, and enables both top and bottom surface connections. This multi-functionality replaces what would traditionally require multiple separate grounding pads, thereby reducing the total area needed while maintaining or improving grounding performance.
2Object-affected harmful factors
If multiple grounding metal pads are used on the guard ring, then spurious signal blocking is improved, but bonding costs increase
Solution Approach 1:
By extending grounding connections through the substrate vertically rather than only horizontally on the surface, the invention achieves effective spurious signal blocking with fewer bonding locations. The through-substrate via structure creates a continuous grounding path that blocks spurious signals without requiring multiple separate pad bonding operations.
Solution Approach 2:
The invention merges multiple grounding functions into a single integrated through-substrate via structure. Instead of requiring multiple separate grounding pads that would each need individual bonding, the through-substrate via combines grounding, shielding, and connection functions into one structure, thereby reducing bonding complexity and cost.
3Area of stationary object
If the number of grounding pads is reduced to minimize chip size, then chip area and bonding costs are reduced, but grounding performance and spurious signal blocking are degraded
Solution Approach 1:
The invention compensates for reduced pad count by utilizing the vertical dimension through through-substrate vias. These vias extend grounding connections from the top surface through the substrate to the bottom surface, creating effective grounding paths without requiring multiple horizontal pads, thus maintaining grounding performance while minimizing chip area.
Solution Approach 2:
The invention changes the geometric parameters of the grounding structure from shallow planar pads to deep vertical through-substrate vias. This parameter change increases the effective grounding path length and connection efficiency, allowing adequate grounding performance to be achieved with fewer structures, thereby reducing the required chip area.
Data Source
AI summary
At least one through-substrate via is formed around the periphery of a semiconductor chip or a semiconductor chiplet included in a semiconductor chip. The at least one through-substrate via may be a single through-substrate via that laterally surrounds the semiconductor chip or the semiconductor chiplet, or may comprise a plurality of through-substrate vias that surrounds the periphery with at least one gap among the through-substrate vias. A stack of back-end-of-line (BEOL) metal structures that laterally surrounds the semiconductor chip or the semiconductor chiplet are formed directly on the substrate contact vias and electrically connected to the at least one through-substrate via. A metallic layer is formed on the backside of the semiconductor substrate including the at least one through-substrate via. The conductive structure including the metallic layer, the at least one through-substrate via, and the stack of the BEOL metal structures function as an electrical ground built into the semiconductor chip.