TSV Chip Stack Package With Selective Rewiring For Chip Selection
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Solution Overview
Problem
Conventional chip stack packages face limitations in operational speed, size miniaturization, and height reduction due to metal wire connections, and TSV chip stack packages lack a mechanism for chip selection, necessitating a novel connection structure to facilitate efficient chip selection without increasing package size.
Innovation Solution
A TSV chip stack package with through silicon vias and rewirings connecting chip selection pads and vias in unique structures for each chip, allowing differential signal application to enable chip selection without additional pads, thereby reducing package size and enhancing operational speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If TSV chip stack package is used to reduce package size and height, then operational speed is improved and miniaturization is achieved, but chip selection capability is lost
Solution Approach 1:
The patent divides the chip stack into multiple independently selectable chips by creating distinct TSV connection paths for each chip. Each chip has its own set of TSVs that can be selectively connected to the substrate, allowing individual chip selection without affecting other chips in the stack. This segmentation enables chip selection capability while maintaining the compact TSV architecture.
Solution Approach 2:
The patent introduces a new dimensional approach by implementing selective TSV connection mechanisms that operate in the vertical stacking dimension. By controlling which TSVs are connected to the substrate through switchable connections or selective bonding, the system enables chip selection along the vertical axis without requiring additional lateral space, thus maintaining miniaturization while adding selection capability.
2Adaptability or versatility
If additional chip selection pads are added to enable chip selection, then chip selection capability is improved, but chip size increases
Solution Approach 1:
The patent makes the existing TSV structures serve multiple functions: they simultaneously provide electrical connection for signal transmission and enable chip selection through selective connectivity. The same TSVs that connect chips to the substrate for normal operation are also used as selection paths, eliminating the need for separate dedicated selection pads and maintaining compact chip size.
Solution Approach 2:
The patent merges the chip selection function with the existing TSV connection structure. Instead of creating separate selection pads and selection paths, the invention combines both functions into the same TSV architecture, where the connectivity of TSVs is controlled to achieve both signal transmission and chip selection simultaneously, thereby avoiding additional area requirements.
3Adaptability or versatility
If wire bonding is used to connect chips to substrate, then chip selection can be implemented, but package height and size increase
Solution Approach 1:
The patent replaces the mechanical wire bonding system with a TSV-based vertical connection system. Instead of using external wires that extend outward from the chip surfaces to create selection paths, the invention uses internally formed TSVs that penetrate the chip substrate vertically, eliminating the need for external wire bonds and reducing package height while maintaining selection capability through electronic switching of TSV connections.
Data Source
AI summary
A through silicon via chip stack package includes a substrate; a plurality of chips stacked over the substrate and provided with chip selection pads, through silicon vias and rewirings connecting the chip selection pad and the through silicon via respectively, the through silicon via being connected to one another; and outside connection terminals attached to a lower surface of the substrate, wherein the rewirings in each of stacked chips are formed so as to have connection structures between the chip selection pads and the through silicon vias which are different from one another in each of the chips.