Wafer-Level TSV Defect Detection via Bias Voltage Barrier Reduction
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Solution Overview
Problem
Conventional integrated circuits face defects in through silicon vias (TSVs) during the formation process, which are difficult to detect until the package level, leading to increased costs and time, as current methods lack effective solutions for identifying and addressing these defects at the wafer level.
Innovation Solution
An integrated circuit design that includes a semiconductor substrate with a through silicon via, a first well region doped with a specific impurity, and a current path providing unit that applies a bias voltage to reduce the potential barrier between the substrate and the TSV, allowing for current flow to an output pad during a test mode, enabling detection of TSV defects at the wafer level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional TSV formation process is used, then TSV structure is completed, but TSV defects cannot be detected until package level
Solution Approach 1:
The patent applies preliminary action by forming a test circuit within the semiconductor substrate before TSV formation that enables pre-detection of TSV defects. The test circuit includes a test pad, test line, and test transistor configured to detect open circuits and short circuits in TSVs before package assembly, allowing defects to be identified at the wafer level rather than at the later package level.
Solution Approach 2:
The patent uses an intermediary approach by introducing a test circuit as a mediator between the TSV structure and the detection process. The test circuit acts as an intermediary system that translates TSV defect conditions (open circuits, short circuits) into detectable electrical signals, enabling indirect detection of TSV defects through the test circuit's response.
2Reliability
If conventional TSV formation process is used, then TSV structure is completed, but detection requires package level inspection increasing costs
Solution Approach 1:
The patent performs preliminary defect detection at the wafer level before package assembly, avoiding the need for costly package-level inspection. By detecting TSV defects early in the manufacturing process through the integrated test circuit, the system prevents defective packages from being assembled, thereby reducing overall manufacturing costs.
Solution Approach 2:
The test circuit is self-contained within the semiconductor substrate and can autonomously detect TSV defects without requiring external specialized equipment or additional manufacturing steps. The test circuit uses the substrate's own power supply and signal lines to perform detection, making the manufacturing process self-sufficient for quality control.
3Reliability
If no test circuit is formed, then device complexity is low, but TSV defects remain undetected
Solution Approach 1:
The patent segments the semiconductor substrate into distinct functional regions: a first region containing the main circuit and a second region containing the test circuit. This segmentation allows the test circuit to be added as a separate functional module without significantly impacting the main circuit's design or operation, thereby minimizing the overall complexity increase while enabling defect detection.
Solution Approach 2:
The test circuit is localized to a specific region (second region) of the semiconductor substrate, separate from the main circuit area. This local placement allows the detection function to be added without requiring system-wide changes, and the test circuit can be activated only when needed, maintaining simplicity in the main operational paths while providing enhanced reliability through localized testing capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the detection of TSV defects at the wafer level, reducing manufacturing costs and time by identifying unsatisfactory TSVs before package assembly, thereby improving the reliability and efficiency of the semiconductor packaging process.
Implementation Method 1
A first bias voltage is applied to a first well region of the semiconductor substrate during the test mode, and the first bias voltage is greater than a potential barrier between the semiconductor substrate and the through silicon via
Data Source
AI summary
An integrated circuit that detects whether a through silicon via has defects or not, at a wafer level. The integrated circuit includes a semiconductor substrate, a through silicon via configured to be formed in the semiconductor substrate to extend to a certain depth from the surface of the semiconductor substrate, an output pad, and a current path providing unit configured to provide a current, flowing between the semiconductor substrate and the through silicon via, to the output pad during a test mode.