Wafer-Level TSV Connection Detection via Overlying Power Lines
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Solution Overview
Problem
Conventional semiconductor devices cannot detect defective Through Silicon Via (TSV) connections at the wafer level, leading to unnecessary costs and extended fabrication processes due to defective chip-to-chip connections only being identified after packaging.
Innovation Solution
A semiconductor device design that includes a first and second power line overlying the TSV, with the first power line connected to a power-supply voltage and the second power line to ground voltage, allowing for current detection between them to identify defective TSV connections before packaging, using a test unit to select power sources and determine connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional TSV structure is used without additional power lines, then device complexity is reduced, but defective TSV connections cannot be detected at wafer level
Solution Approach 1:
The power supply structure is segmented into two separate power lines (first power line and second power line) that are positioned to overlie the TSV. This segmentation allows independent testing of TSV connectivity by selectively connecting power sources to different lines, enabling defective TSV detection without requiring complex multi-layer test structures.
Solution Approach 2:
The first and second power lines act as intermediary test structures that mediate between the test unit and the TSV connection. By routing power sources through these intermediate power lines, the system can detect TSV defects without directly probing the TSV itself, simplifying the overall test architecture while maintaining detection capability.
2Productivity
If wafer-level TSV detection is implemented, then productivity is improved by avoiding packaging of defective chips, but device complexity increases due to additional power lines
Solution Approach 1:
The first and second power lines are formed during the wafer fabrication process before packaging, enabling preliminary detection of TSV defects. This preliminary action allows defective chips to be identified and removed early in manufacturing, improving productivity by preventing unnecessary packaging operations while adding only minimal structural complexity.
Solution Approach 2:
The power lines serve dual functions: they provide power supply to the device and simultaneously serve as test structures for detecting TSV connectivity. This multi-functionality eliminates the need for separate dedicated test structures, improving productivity while keeping the added complexity minimal.
3Measurement precision
If first and second power lines are formed overlying the TSV, then measurement precision of TSV connectivity is improved, but device complexity increases
Solution Approach 1:
The first and second power lines are positioned to specifically overlie the TSV region, creating a localized test structure with high measurement precision for TSV connectivity. The power lines have different widths and are strategically positioned to maximize sensitivity to TSV defects while minimizing impact on overall device complexity.
Solution Approach 2:
The power lines are designed with partial overlap over the TSV region rather than complete coverage, providing sufficient measurement precision for defect detection without requiring excessive structural complexity. The selective positioning of power lines over critical TSV areas achieves high detection precision with minimal added complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables pre-packaging detection of defective TSV connections, reducing unnecessary costs and time by verifying chip-to-chip and TSV-chip connectivity at the wafer level, facilitating high-capacity and high-speed DRAM operations.
Implementation Method 1
a first power line and a second power line formed over the TSV in a manner that the first and second power lines overlie the TSV... allowing for current detection between them to identify defective TSV connections
Data Source
AI summary
A semiconductor device is disclosed allowing detection of a connection state of a Through Silicon Via (TSV) at a wafer level. The semiconductor device includes a first line formed over a Through Silicon Via (TSV), a second line formed over the first line, and a first power line and a second power line formed over the same layer as the second line. Therefore, the semiconductor device can screen not only a chip-to-chip connection state after packaging completion, but also a connection state between the TSV and the chip at a wafer level, so that unnecessary costs and time encountered in packaging of a defective chip are reduced.