Semiconductor Package TSV Exposure via Bonding Layer Etching

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Solution Overview

Problem

There is a need for technologies that prevent physical defects and electrical deterioration in semiconductor packages during the stacking process, while maintaining reliability and reducing production costs.

Innovation Solution

A method of manufacturing semiconductor packages involves forming a bonding layer on a carrier substrate, bonding an inner substrate to it, removing the carrier substrate, and using the remaining bonding layer as a gap-filling portion to expose solder balls, which are then thermocompression bonded to a package substrate, with additional steps including grinding and chemical mechanical polishing to expose TSVs and form pads for electrical connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the bonding layer is completely removed to expose solder balls for mounting, then electrical connectivity is achieved, but the structural support and alignment are lost

Engineering Contradiction:
Improveelectrical connectivityVSAvoidstructural support
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The bonding layer is partially removed rather than completely removed. The etching process is controlled to expose the solder balls while leaving portions of the bonding layer intact to maintain structural support and alignment between the inner substrate and carrier substrate during the mounting process.

Inventive Principle:
Principle #16Partial or excessive action

2Manufacturing precision

If multiple separate processes are used for bonding layer removal and gap-filling, then precise control is achieved, but production complexity and costs increase

Engineering Contradiction:
Improvebonding layer removal precisionVSAvoidproduction process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The bonding layer removal process and gap-filling process are merged into a single integrated process. The etching solution simultaneously removes the bonding layer to expose solder balls and fills gaps in the bonding layer structure, eliminating the need for separate processing steps and reducing production complexity.

Inventive Principle:
Principle #5Merging (Combining)

3Ease of manufacture

If the bonding layer is used as gap-filling portion, then production costs are reduced, but adhesion stability must be maintained

Engineering Contradiction:
Improveproduction costVSAvoidadhesion stability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The bonding layer serves multiple functions: it initially bonds the inner substrate to the carrier substrate, then after partial removal it acts as the gap-filling portion during mounting. This multi-functionality reduces the need for separate materials and processes, lowering production costs while maintaining adhesion stability through proper material selection and process control.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method enhances the reliability of semiconductor packages by preventing defects and reducing production costs by utilizing the bonding layer as a gap-filling portion, ensuring stable adhesion and electrical connectivity.

Implementation Method 1

forming a bonding layer on a carrier substrate, bonding an inner substrate and the carrier substrate with the bonding layer

Methodology Applied
Scientific EffectAdhesion: Adhesive

Implementation Method 2

mounting the inner substrate on a package substrate by performing thermocompression bonding

Methodology Applied
Scientific EffectThermocompression bonding:

Implementation Method 3

the grinding of the upper surface of the inner substrate by a chemical mechanical polishing (CMP) process

Methodology Applied
Scientific EffectChemical mechanical polishing:

Data Source

PatentUS9728424B2Method of fabricating a packaged integrated circuit with through-silicon via an inner substrate
Publication Date: 2017.08.08 SAMSUNG ELECTRONICS CO LTD
  • US9728424B2 patent drawing
  • US9728424B2 patent drawing
  • US9728424B2 patent drawing

AI summary

A method of manufacturing a semiconductor package includes forming a bonding layer on a carrier substrate, bonding an inner substrate to the carrier substrate, removing the carrier substrate, and forming a gap-filling portion by removing a portion of the bonding layer to expose a portion of a solder ball provided in the inner substrate. The inner substrate may be mounted on a package substrate and a semiconductor chip may be mounted on the inner substrate.