3D IC Stacking with TSVs and Fan-Out Redistribution
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Solution Overview
Problem
The semiconductor industry faces challenges in packaging smaller semiconductor dies with increasing numbers of input/output pads, as traditional two-dimensional integration approaches reach physical limits, necessitating the development of three-dimensional integrated circuits (3D ICs) with through-silicon vias (TSVs) for enhanced density and functionality.
Innovation Solution
The implementation of 3D ICs with TSVs, where two or more wafers with integrated circuits are bonded, and a redistribution structure with TSVs is used to provide electrical connections and heat dissipation, along with a redistribution structure that enables fan-out beyond the edges of the dies, and a protective layer to secure external connectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional two-dimensional integration approaches are used, then manufacturing simplicity is maintained, but integration density reaches physical limits and packaging becomes increasingly difficult
Solution Approach 1:
The patent transitions from two-dimensional integration to three-dimensional integrated circuits by stacking multiple semiconductor dies vertically and establishing electrical connections through through-silicon vias (TSVs) that penetrate the substrate thickness, thereby increasing integration density while managing packaging complexity through structured vertical interconnections
2Adaptability or versatility
If more functions are integrated into smaller semiconductor dies, then functional density improves, but the number of I/O pads increases and packaging becomes more challenging
Solution Approach 1:
The patent resolves the I/O pad packaging challenge by moving interconnections to the vertical dimension through TSVs, allowing I/O pads to be distributed across multiple stacked dies rather than concentrated on a single die surface, thereby reducing the packaging burden on individual dies while maintaining high functional density
Solution Approach 2:
The patent divides the integrated circuit functionality across multiple separate semiconductor dies that are stacked and interconnected, allowing each die to have fewer I/O pads and simpler packaging requirements while the overall system achieves high functional density through the stacked configuration
3Quantity of substance
If three-dimensional integrated circuits with TSVs are implemented, then integration density increases, but manufacturing process complexity increases
Solution Approach 1:
The patent forms through-silicon vias (TSVs) and applies conductive materials to substrate surfaces before bonding the semiconductor dies together, allowing precise alignment and reliable electrical connections while simplifying the overall manufacturing process compared to forming vias after bonding
Data Source
AI summary
A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer are provided. In some embodiments, the semiconductor package has a plurality of through substrate vias (TSVs) extending through an interposer substrate. A redistribution structure is arranged over a first surface of the interposer substrate, and a first die is bonded to the redistribution structure. An edge of the first die is beyond a nearest edge of the interposer substrate. A second die is bonded to the redistribution structure. The second die is laterally separated from the first die by a space.