TSV Metal Gettering Dielectric Liners for Copper Diffusion Control
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Solution Overview
Problem
Through-substrate vias (TSVs) in integrated circuits (ICs) face issues with diffusion barrier layer integrity due to sidewall planarity aberrations, leading to potential metal filler escape from the semiconductor, which degrades minority carrier lifetimes and transistor performance.
Innovation Solution
Incorporating a metal gettering agent into the dielectric liner of TSVs, such as fluorine or elements from Group 15, to provide a secondary line of defense against metal filler escape, particularly for fast-diffusing metals like copper, enhancing diffusion barrier integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a diffusion barrier layer is deposited on the dielectric liner to prevent metal escape, then metal filler containment is improved, but sidewall planarity aberrations cause non-uniform barrier layer thickness leading to localized escape paths
Solution Approach 1:
The patent introduces a gettering agent at specific locations within the dielectric liner (particularly at the TSV tip and along the sidewalls) to provide localized metal trapping capability. This addresses the non-uniform barrier layer by creating concentrated gettering zones where metal escape is most likely to occur, rather than requiring uniform barrier properties throughout the entire structure.
Solution Approach 2:
The gettering agent acts as an intermediary layer between the diffusion barrier and the semiconductor substrate. When metal fills escape through defects in the diffusion barrier, the gettering agent intercepts these metal atoms and traps them within the dielectric liner, preventing them from reaching and degrading the semiconductor material.
2Reliability
If conventional dielectric liner materials (silicon oxide, silicon nitride) are used, then electrical isolation is provided, but metal filler escape into the semiconductor degrades minority carrier lifetimes
Solution Approach 1:
The patent creates a composite dielectric liner structure by incorporating gettering agents (such as phosphorus, arsenic, or antimony) into conventional dielectric materials like silicon oxide or silicon oxynitride. This composite structure maintains the electrical isolation properties of the base dielectric while adding metal-trapping functionality through the gettering agent, thereby preventing metal escape without compromising electrical performance.
Solution Approach 2:
The patent converts the potential harm of metal filler escape into a beneficial trapping mechanism. By intentionally introducing gettering agents that have high affinity for metal atoms, the system transforms the risk of metal contamination into a controlled metal-trapping function, where escaped metal is captured and immobilized rather than allowing it to reach and degrade the semiconductor.
3Ease of manufacture
If PVD processes are used to deposit diffusion barrier layers, then manufacturing cost is reduced, but sidewall planarity aberrations result in poor barrier layer integrity
Solution Approach 1:
The patent implements a two-layer protection system: first, the diffusion barrier layer is deposited to provide primary metal containment, and second, the gettering agent within the dielectric liner serves as a backup safety mechanism. This beforehand cushioning ensures that even if the PVD-deposited barrier layer has integrity issues due to sidewall planarity problems, the gettering agent will catch any escaping metal, maintaining overall system reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The metal gettering agent effectively traps and prevents the escape of metal fillers like copper, maintaining minority carrier lifetimes and improving IC performance by reducing transistor degradation.
Implementation Method 1
forming a dielectric liner to frame sidewalls and a bottom of the plurality of vias, wherein the dielectric liner includes at least a portion having at least one metal gettering agent
Data Source
AI summary
An IC includes a substrate having a semiconductor top surface and a bottom surface, wherein the semiconductor top surface includes one or more active circuit components and a plurality of through silicon vias (TSVs) extending through the substrate. The plurality of TSVs include an outer dielectric liner. The dielectric liner includes at least one halogen or a Group 15 element metal gettering agent in an average concentration from 1 to 10 atomic %. A metal diffusion barrier layer is on the dielectric liner and a metal filler is on the metal barrier layer. The metal gettering agent getters metal filler that escapes the metal barrier layer.