TSV Hillock Suppression via Diffusion Barrier
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Solution Overview
Problem
Thermal stress-induced hillocks form on via-middle metal through-silicon vias (TSVs) due to the difference in thermal expansion coefficients between the filler metal and the silicon substrate, interfering with subsequent processing and causing defects in integrated circuits (ICs).
Innovation Solution
An electrically conductive hillock suppression structure is applied to the polished top surface of TSVs, either by forming a silicon or germanium doped region or a silicide, or depositing a metal layer with a different composition, to block fast diffusion paths and suppress hillock formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper filler metal is used in via-middle TSV processes, then electrical conductivity is improved, but thermal stress-induced hillocks form on the TSV surface
Solution Approach 1:
A diffusion barrier layer is introduced as an intermediary between the copper filler metal and the silicon substrate. This barrier layer prevents copper atoms from diffusing to the TSV surface while allowing electrical current to pass through, thereby eliminating hillock formation without compromising electrical conductivity
Solution Approach 2:
The chemical composition and crystal structure parameters of the TSV surface are modified by forming a controlled surface layer or doping the copper with other elements. This changes the surface energy and diffusion characteristics, preventing hillock formation while maintaining bulk electrical conductivity
2Stress or pressure
If hillocks are allowed to form, then stress relief occurs, but subsequent BEOL processing is interfered with and defects are created
Solution Approach 1:
The diffusion barrier layer serves as a mediator that allows stress relief to occur through controlled mechanisms without allowing uncontrolled copper diffusion to the surface. This maintains processing quality by preventing hillock formation that would interfere with BEOL processing
Solution Approach 2:
The diffusion barrier layer is applied in advance during TSV formation, before subsequent BEOL processing steps. This preliminary protective action prevents hillock formation that would otherwise occur during later high-temperature processing, ensuring processing quality throughout manufacturing
3Manufacturing precision
If diffusion paths are blocked to suppress hillocks, then manufacturing precision is improved, but electrical conductivity may degrade
Solution Approach 1:
The diffusion barrier is applied locally only at the TSV surface where hillock formation occurs, rather than throughout the entire TSV structure. This localized approach blocks diffusion paths at the surface to maintain flatness while leaving the bulk copper conductivity unchanged
Solution Approach 2:
The barrier layer is designed with specific thickness and material properties that allow it to be sufficiently thick to block diffusion paths and maintain surface flatness, yet thin enough to maintain low electrical resistance. Material selection and thickness optimization balance these competing requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The suppression structure effectively reduces hillock formation, improving the yield and reliability of TSV ICs by preventing topography-related defects and maintaining minimal resistivity increase, thus enabling reliable via-middle Cu TSVs without significant performance degradation.
Implementation Method 1
Blocking the fast diffusion paths restricts diffusion of fast diffusing metals such as Cu to the TSV free surface, thereby suppressing hillock formation
Implementation Method 2
the hillock suppression is achieved by reacting the Cu at the TSV free surface with silane to form a silicon doped region or a silicide at the exposed top TSV surface
Implementation Method 3
the silicide generally dissolves into the bulk Cu of the TSV to form a solid solution comprising atomic silicon during subsequent exposure to moderate temperatures
Data Source
AI summary
A method for fabricating integrated circuit (ICs) having through substrate vias (TSVs) includes forming active circuit elements on a semiconductor wafer and then forming a plurality of embedded vias through the top side of the wafer. A metal filler layer including a filler metal is deposited to fill the embedded vias. Chemical mechanical polishing (CMP) then forms a plurality of embedded TSVs that have polished top TSV surfaces having exposed filler metal. An electrically conductive hillock suppression structure is formed by forming a silicon or germanium doped region, or a silicide or germanicide at the polished top TSV surface or by forming a metal layer on the polished top TSV surface having a composition different from the filler metal. A dielectric layer is deposited on the semiconductor wafer including over the hillock suppression structure. The dielectric layer is removed over the polished top TSV surface to allow metal contact thereto.