On-Chip Inductor Q Improvement via TSV Grounding Fence
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Solution Overview
Problem
The performance of on-chip inductors is degraded due to energy dissipation in semiconductor substrates at high frequencies, leading to poor quality factor (Q) and noise coupling, which is not effectively addressed by traditional patterned-ground-shielding structures.
Innovation Solution
The use of through-silicon-vias (TSVs) formed through the semiconductor substrate, coupled to a metallized backside for grounding, provides isolation to on-chip inductors, and can be combined with traditional patterned-ground-shielding structures to enhance the quality factor (Q) and reduce noise coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional patterned-ground-shielding structures are used to provide decoupling, then some isolation is achieved, but the quality factor (Q) improvement is limited and optimized widths and spacings are difficult to find
Solution Approach 1:
The patent transitions from planar patterned-ground-shielding structures to three-dimensional cavity structures formed by through-silicon-vias. This vertical dimensionality change creates effective electromagnetic isolation without requiring complex planar optimization of widths and spacings, directly improving Q factor while reducing design complexity
2Area of stationary object
If the inductor is placed on the semiconductor substrate, then chip area is utilized, but energy dissipation occurs in the substrate at high frequencies degrading performance
Solution Approach 1:
The patent segments the electromagnetic field distribution by creating localized cavity structures around the inductor using through-silicon-vias. This segmentation confines the magnetic field within the cavity region, preventing energy dissipation into the surrounding substrate while maintaining compact chip area utilization
Solution Approach 2:
The through-silicon-via cavity structures act as intermediary elements between the inductor and the substrate. These cavities serve as electromagnetic isolation barriers that prevent direct coupling between the inductor and lossy substrate, reducing energy dissipation while allowing the inductor to remain on-chip
3Productivity
If the inductor occupies substantial chip area, then RF and microwave functions are achieved, but noise coupling via the substrate increases
Solution Approach 1:
By introducing vertical cavity structures through the silicon substrate using through-silicon-vias, the patent creates three-dimensional electromagnetic isolation zones. This dimensional approach effectively suppresses substrate noise coupling paths while preserving the inductor's RF and microwave functionality, without requiring increased chip area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The TSV-based shielding structure improves the quality factor (Q) of on-chip inductors by reducing energy dissipation and noise coupling, offering better isolation and suppression of unwanted modes, and can be applied in various chip stacking configurations.
Implementation Method 1
a plurality of through-silicon-vias formed through the first semiconductor substrate in a vicinity of the one or more on-chip inductors, and one or more conductors coupling at least one of the plurality of through-silicon-vias to a ground
Data Source
AI summary
A semiconductor structure for providing isolations for on-chip inductors comprises a semiconductor substrate, one or more on-chip inductors formed above the first semiconductor substrate, a plurality of through-silicon-vias formed through the first semiconductor substrate in a vicinity of the one or more on-chip inductors, and one or more conductors coupling at least one of the plurality of through-silicon-vias to a ground, wherein the plurality of through-silicon-vias provide isolations for the one or more on-chip inductors.