Semiconductor TSV Formation via Insulating Etch Stopper
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Solution Overview
Problem
The BSV method for forming TSVs in semiconductor devices faces challenges due to variations in semiconductor substrate thickness, leading to inconsistent hole formation and reduced reliability due to side etching and inadequate coverage of conductive material.
Innovation Solution
A manufacturing method that forms an insulating layer as an etching stopper on the front side of the semiconductor substrate with a pre-formed opening, allowing for selective etching from the rear side to create holes that are larger than the opening, ensuring self-alignment and preventing side etching by maintaining the insulating layer as a barrier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the BSV method is adopted to form TSVs, then high-speed large-capacity memory chips can be realized, but variations in thickness of the semiconductor substrate cause inconsistent hole formation and degradation in reliability
Solution Approach 1:
The patent applies preliminary action by forming the insulating layer with an opening on the front surface of the semiconductor substrate before forming holes from the rear surface. This pre-formed insulating layer structure serves as a depth reference and etching stopper, ensuring that holes are formed to the correct depth even when substrate thickness varies, thereby resolving the inconsistency in hole formation caused by thickness variations.
Solution Approach 2:
The patent introduces an insulating layer as an intermediary element between the front surface LSI and the rear surface holes. This insulating layer with a pre-formed opening acts as a mediator that guides hole formation, providing a physical reference structure that ensures consistent hole depth and positioning despite variations in substrate thickness, thus improving both reliability and manufacturing precision.
2Productivity
If holes are formed on one chip at the same time, then productivity is improved, but side etching occurs and coverage of conductive material becomes insufficient
Solution Approach 1:
The insulating layer with a pre-formed opening acts as an intermediary that prevents side etching when holes are formed simultaneously on one chip. The insulating material forms a protective barrier around the hole formation area, confining the etching process to the intended path and preventing lateral etching that would compromise conductive material coverage, thereby maintaining reliability while enabling high productivity.
Solution Approach 2:
The insulating layer structure serves a dual function: it guides hole formation and simultaneously protects against side etching. The pre-formed opening in the insulating layer self-aligns with the hole formation process, and the insulating material automatically provides protection during etching, eliminating the need for additional protective measures and enabling reliable simultaneous hole formation across the chip.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures precise and reliable formation of TSVs by preventing side etching and maintaining adequate coverage of the conductive material, enhancing the reliability of the semiconductor device.
Implementation Method 1
forming an insulating layer with an opening on a first surface of a semiconductor substrate; forming a hole extending from a second surface of the semiconductor substrate to the conductive layer through the opening by selectively etching the semiconductor substrate from the second surface
Data Source
AI summary
According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface, and having a LSI on the first surface of the semiconductor substrate, a first insulating layer with an opening, the first insulating layer provided on the first surface of the semiconductor substrate, a conductive layer on the opening, the conductive layer being connected to the LSI, and a via extending from a second surface of the semiconductor substrate to the conductive layer through the opening, the via having a size larger than a size of the opening in a range from the second surface to a first interface between the semiconductor substrate and the first insulating layer, and having a size equal to the size of the opening in the opening.