3D Semiconductor Device With TSV Interconnects
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and low flexibility, limiting the production of commercially viable logic families with diverse products, and struggle with inter-chip interconnects, which dominate IC performance and power consumption.
Innovation Solution
The development of a 3D IC technology using Through-Silicon-Via (TSV) connections and a method for constructing configurable logic devices with antifuse programmability, allowing for modular construction of logic, memory, I/O, and analog functions, and reducing the size and number of TSVs to enhance connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If current semiconductor fabrication methods are used, then manufacturing process is established, but mask-set costs are high and flexibility is low
Solution Approach 1:
The patent segments the semiconductor fabrication process into modular components: through-silicon via formation, metal layer deposition, and transistor fabrication can be independently optimized and reconfigured. This modular approach allows different process combinations for different products, reducing mask-set requirements while maintaining manufacturing efficiency.
Solution Approach 2:
The patent transitions from planar 2D IC architecture to 3D stacked architecture with through-silicon vias enabling vertical interconnects. This dimensional change allows multiple logic families and product types to coexist on the same wafer substrate, significantly improving flexibility without requiring separate fabrication lines for each product type.
2Reliability
If traditional IC interconnect methods are used, then connectivity is established, but inter-chip interconnects dominate power consumption and reduce performance
Solution Approach 1:
The patent implements 3D stacked architecture with through-silicon vias that enable vertical inter-chip connections. This reduces the horizontal distance for signal transmission compared to traditional planar interconnects, lowering resistance and capacitance, thereby reducing power consumption while improving signal integrity and overall IC performance.
Solution Approach 2:
The patent introduces metal layers and through-silicon via structures as intermediary conductive pathways between chips. These optimized interconnect structures replace traditional high-power-consuming wire bonds or PCB traces, providing lower-resistance pathways that reduce power loss and improve performance.
3Productivity
If TSV size is reduced to enhance connectivity, then connection density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes TSV dimensional parameters (diameter, depth, spacing) to achieve high connection density while remaining within manufacturable precision ranges. By carefully selecting TSV size parameters and using appropriate deposition and etching processes, the patent achieves sub-micron TSV dimensions with sufficient yield and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs by minimizing the need for multiple mask sets and enables high-density connections below one micron in size, facilitating the use of 3D IC technology across various device applications while improving IC performance and power efficiency.
Implementation Method 1
performing at least one deposition step to deposit a gate electrode for the second transistors and the third transistors
Data Source
AI summary
A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming peripheral circuitry in and/or on the first level, and includes first single crystal transistors; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming second level disposed on top of the second metal layer; performing a first lithography step; forming a third level on top of the second level; performing a second lithography step; processing steps to form first memory cells within the second level and second memory cells within the third level, where the plurality of first memory cells include at least one second transistor, and the plurality of second memory cells include at least one third transistor; and deposit a gate electrode for second and third transistors simultaneously.