TSV Structure with Lateral Metal Line for Chip Area Reduction
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Solution Overview
Problem
Conventional through-silicon via (TSV) structures in integrated circuits occupy significant chip area and have high manufacturing costs due to the need for large electrode pads and complex patterning of insulating films, limiting integration density and increasing circuit RC delay and power consumption.
Innovation Solution
A novel TSV structure where the TSV is formed spaced apart from the TSV pad, with a metal line electrically connecting them, reducing the need for surrounding pads and simplifying the manufacturing process by using a method involving a diffusion barrier layer, copper seed layer, and selective copper filling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional TSV structure with surrounding electrode pad is used, then electrical connectivity is achieved, but chip area is significantly occupied
Solution Approach 1:
The invention transitions from a two-dimensional planar electrode pad configuration to a three-dimensional structure where the TSV is connected to the pad through a metal line that extends laterally. This allows the TSV to be positioned away from the pad while maintaining electrical connectivity, thereby reducing the area occupied by the pad and improving chip area utilization.
Solution Approach 2:
The electrical connection path is segmented into two distinct parts: a vertical TSV component that provides the through-silicon connection, and a lateral metal line component that connects the TSV to the electrode pad. This segmentation allows the TSV to be positioned independently from the pad, reducing the pad area requirement while maintaining connectivity.
2Ease of manufacture
If conventional TSV formation with multiple insulating films is used, then TSV structure is achieved, but manufacturing cost increases
Solution Approach 1:
The invention extracts and eliminates the complex multi-layer insulating film structure from the conventional TSV formation process. By removing this complex insulation system and replacing it with a simplified structure using available metal lines and existing dielectric layers, the manufacturing process becomes less complex and more cost-effective while still achieving the required TSV functionality.
3Productivity
If more devices are integrated into one chip, then integration density improves, but number and length of interconnections increases
Solution Approach 1:
The invention utilizes the third dimension (vertical depth) by allowing TSVs to extend through the substrate and connect to pads laterally through metal lines. This three-dimensional interconnection approach reduces the need for long lateral interconnections on the chip surface, thereby managing interconnection complexity while maintaining high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces chip area usage, lowers manufacturing costs, and simplifies the process while maintaining effective electrical connectivity, thereby improving integration density and reducing power consumption.
Implementation Method 1
blanket forming a diffusion barrier layer over the wafer, wherein the diffusion barrier layer extends into the TSV opening
Implementation Method 2
forming a metal line electrically connecting the TSV and the TSV pad
Data Source
AI summary
An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a substrate; a through-silicon via (TSV) extending into the substrate; a TSV pad spaced apart from the TSV; and a metal line over, and electrically connecting, the TSV and the TSV pad.