TSV Multi-Chip Package for Signal Reliability
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Solution Overview
Problem
Conventional multi-chip packages with vertically stacked semiconductor chips face increased footprint and signal transfer issues due to edge interconnection, leading to power over-consumption and reliability concerns, particularly with gold wire arrays causing signal skew.
Innovation Solution
A multi-chip package utilizing through-silicon-via (TSV) for vertical interconnections between semiconductor chips, enabling high-speed operation with reduced interconnection distance and minimizing size, while allowing for selective activation of slice chips without adding additional TSVs through a controller-managed activation mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gold wire is arrayed between pads to improve signal quality, then signal quality is improved, but transfer speed is lowered and signal skew occurs
Solution Approach 1:
The patent replaces the mechanical wire interconnection system with a direct pad-to-pad contact system. Instead of using gold wires that physically connect pads across chips, the invention enables direct electrical contact between pads of stacked chips, eliminating the mechanical wire component and its associated inductance and resistance that limit signal speed and quality.
2Reliability
If interconnection is arrayed along edge of semiconductor chips, then signal transfer is enabled, but area of chips is increased and interposer layer is requested
Solution Approach 1:
The patent transitions from two-dimensional edge-based interconnection to three-dimensional face-based interconnection. Instead of arraying interconnections along the edges of chips in a planar configuration, the invention stacks chips vertically and enables interconnections through the faces of the chips, utilizing the third dimension (vertical stacking) to achieve compact integration without increasing chip area.
3Adaptability or versatility
If multiple TSVs are added to enable flexible activation modes, then activation flexibility is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent makes the existing TSV structure multi-functional by enabling it to serve different purposes based on activation modes. The same TSV infrastructure supports both 3DS mode (where all chips are activated) and QDP mode (where specific chip combinations are activated), eliminating the need for additional dedicated interconnections for each mode while maintaining full flexibility.
Data Source
AI summary
A multi-chip package having a plurality of slice chips coupled through a through-via, at least one slice chip may include an input unit suitable for receiving a slice activation signal, and outputting the slice activation signal to the through-via in response to a slice identification corresponding to the slice chip, a first output unit suitable for outputting the activation signal transferred through the through-via to an internal circuit of the slice chip in response to the corresponding slice identification, and a second output unit suitable for selectively outputting the activation signal transferred through the through-via to the internal circuit of the slice chip in a predetermined activation mode for the multi-chip package.