Low-Temperature TSV Fabrication via PECVD Oxide Liner
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Solution Overview
Problem
Conventional through-silicon via (TSV) fabrication processes face challenges due to the thermal degradation of bonding adhesives at temperatures above 250°C, leading to breakage or failure of TSV circuits during high-temperature material deposition processes.
Innovation Solution
A method involving the deposition of an oxide liner using tetraethylorthosilane and oxygen gas in a plasma-enhanced chemical vapor deposition process at temperatures below 250°C, along with the use of silicon nitride passivation layers to stabilize the substrate and prevent adhesive degradation, ensuring the integrity of TSVs during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional high-temperature deposition processes are used to deposit dielectric materials into TSV features, then material deposition quality is improved, but the bonding adhesive deteriorates due to temperatures exceeding 250°C, causing TSV circuit breakage or failure
Solution Approach 1:
The patent changes the temperature parameter from conventional high-temperature processing (>250°C) to low-temperature processing (<250°C). This is achieved by using plasma-enhanced chemical vapor deposition (PECVD) with modified process parameters including reduced RF power, adjusted gas flow rates, and optimized pressure conditions, allowing dielectric deposition to proceed at temperatures that preserve adhesive integrity while maintaining deposition quality
Solution Approach 2:
The patent introduces a low-temperature PECVD process as an intermediary method between the conflicting requirements of high-quality dielectric deposition and adhesive preservation. This intermediary process uses plasma activation to enable dielectric material deposition at reduced temperatures, serving as a bridge that satisfies both the deposition quality requirement and the adhesive stability requirement
2Strength
If the silicon wafer is bonded to the support panel using bonding adhesive, then the fragile silicon wafer is protected during fabrication, but the adhesive bond fails at temperatures above 250°C during dielectric deposition
Solution Approach 1:
The patent modifies the processing temperature parameter to remain below 250°C throughout the dielectric deposition process. This temperature parameter change preserves the bonding adhesive integrity while maintaining sufficient thermal energy for dielectric material deposition through plasma enhancement, thereby protecting the wafer-bond structure from thermal degradation
3Reliability
If conventional wire bonding is used to connect features of vertically stacked substrates, then electrical connections are formed, but the circuit area increases and areal density decreases
Solution Approach 1:
The patent extracts the electrical connection function from the lateral wire bonding approach and relocates it to vertical through-silicon vias. By etching conductive pathways directly through the substrate thickness, the connection is moved from the perimeter (wire bonds) to the interior (TSVs), eliminating the need for lateral connection space and reducing overall circuit area while maintaining electrical connectivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the successful fabrication of TSVs with improved adhesive stability and reduced risk of substrate damage, enabling the formation of high-quality TSVs with enhanced electrical isolation and moisture resistance.
Implementation Method 1
energizing the deposition gas to form a plasma by applying a current at a first frequency to the process electrodes
Implementation Method 2
deposition of an oxide liner using tetraethylorthosilane and oxygen gas in a plasma-enhanced chemical vapor deposition process
Data Source
AI summary
A through-silicon via fabrication method includes etching a plurality of through holes in a silicon plate. An oxide liner is deposited on the surface of the silicon plate and on the sidewalls and bottom wall of the through holes. A metallic conductor is then deposited in the through holes. In another version, which may be used concurrently with the oxide liner, a silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate.