3D Stacked Chip TSV Scan Circuit for Open and Short Detection
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Solution Overview
Problem
Existing methods for detecting connection failures in through silicon vias (TSVs) of semiconductor devices struggle to identify short failures, despite being able to detect open failures effectively.
Innovation Solution
A semiconductor device design that includes a base chip and memory chips stacked with signal paths, utilizing PMOS and NMOS transistors to drive and detect logic levels during even and odd scan operations, enabling simultaneous detection of both open and short failures in the signal paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a scan operation is used to detect connection failures in through silicon vias, then open failures can be detected, but short failures cannot be detected
Solution Approach 1:
The patent implements dynamic switching between even and odd scan operations, where the driving transistors (PMOS/NMOS) are selectively activated based on the scan phase. This dynamic operation enables the system to adapt its detection mode to identify different failure types - open failures during one phase and short failures during another phase, thereby achieving comprehensive failure detection coverage
Solution Approach 2:
The patent employs periodic alternating scan operations (even scan and odd scan) to detect different failure types. By periodically switching between these two scan modes, the system can systematically cover both open failures and short failures that would be undetectable in a single static scan mode, thus resolving the limitation of detection versatility
2Productivity
If multiple signal paths are tested simultaneously, then detection efficiency is improved, but the complexity of the detection circuit increases
Solution Approach 1:
The patent merges multiple signal path detections into unified even and odd scan operations. By combining the detection of multiple through silicon vias into single scan phases, the system achieves efficient parallel testing of multiple paths while using shared circuit resources, thereby improving detection efficiency without proportionally increasing circuit complexity
Solution Approach 2:
The scan circuit is designed with universal functionality to handle multiple detection tasks. The same even/odd scan infrastructure can detect both open failures and short failures across multiple signal paths, eliminating the need for separate dedicated circuits for each failure type or path, thus maintaining circuit simplicity while achieving high detection efficiency
Data Source
AI summary
A semiconductor device includes a base chip and a memory chip stacked with first, second, third, and fourth signal paths, each signal path extending through the memory chip into the base chip. The base chip and the memory chip are configured to simultaneously drive the first signal path and the third signal path after the start of an even scan operation and then simultaneously drive the second signal path and the fourth signal path after the start of an odd scan operation. The base chip is configured to generate first, second, third, and fourth fail detection signals that detect a connection failure of the first, second, third, and fourth signal paths based on a logic level at which the first, second, third, and fourth signal paths are driven.