TSV Semiconductor Structure With Doped Stress Buffer Regions
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Solution Overview
Problem
The TSV manufacturing process generates thermal stress due to mismatched thermal expansion coefficients between copper, the substrate, and the dielectric layer, leading to interface cracking and instability in semiconductor structures.
Innovation Solution
A semiconductor structure with a stress buffer structure, including a first buffer doped area formed by doping active areas with a first buffer impurity having an atomic radius smaller than the substrate material, which absorbs thermal stress and buffers expansion stress between the substrate and the through hole structure, improving structural stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If TSV manufacturing process is used to shorten wire length and improve signal speed, then productivity and signal transmission performance are improved, but thermal stress and interface cracking occur due to mismatched thermal expansion coefficients
Solution Approach 1:
A stress buffer structure comprising a first buffer doped area and a second buffer doped area is introduced as an intermediary between the substrate and the through hole structure. The first buffer doped area is formed by doping the substrate with a first buffer impurity having an atomic radius smaller than that of the substrate material, creating compressive stress. The second buffer doped area is formed by doping with a second buffer impurity having an atomic radius larger than that of the substrate material, creating tensile stress. These opposing stresses counterbalance the thermal expansion mismatch between copper and the substrate/dielectric layer, preventing interface cracking while maintaining the TSV structure's signal transmission benefits.
2Reliability
If copper is used to fill through hole structure for low resistance connection, then electrical conductivity is improved, but thermal expansion mismatch causes stress and cracking
Solution Approach 1:
The patent changes the physical and mechanical parameters of the substrate by introducing buffer impurities with different atomic radii. The first buffer impurity (smaller atomic radius) creates compressive stress, while the second buffer impurity (larger atomic radius) creates tensile stress. This parameter change in the substrate's stress state compensates for the thermal expansion coefficient mismatch between copper and the surrounding materials, allowing copper to be used for low-resistance connections without causing interface cracking.
3Manufacturing precision
If shallow trench isolation structure is used to isolate substrate into active areas, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The stress buffer structure is merged with the shallow trench isolation structure by forming the first and second buffer doped areas within the same isolation regions. The buffer doped areas are created during the same processing steps as the shallow trench isolation, combining the isolation function with the stress buffering function in a single integrated structure, thereby reducing overall device complexity while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stress buffer structure effectively reduces thermal stress and enhances the stability of the semiconductor device by introducing local strain that counteracts expansion stress, thereby protecting the semiconductor structure from cracking and improving performance.
Implementation Method 1
The TSV manufacturing process generates thermal stress due to mismatched thermal expansion coefficients between copper, the substrate, and the dielectric layer
Implementation Method 2
The first buffer doped area is arranged in the active areas and formed by doping the active areas with a first buffer impurity
Data Source
AI summary
A semiconductor structure has a first area, a second area and a third area. The second area is arranged between the first area and the third area. The semiconductor structure includes: a substrate; a shallow trench isolation structure arranged in the substrate and configured to isolate the substrate into a plurality of active areas, in which the active areas in the first area form a semiconductor device; a dielectric layer arranged on the substrate; a through hole structure arranged in the third area and penetrating through the dielectric layer and the substrate; and a stress buffer structure arranged in the second area and including a first buffer doped area, in which the first buffer doped area is arranged in the active areas and formed by doping the active areas with a first buffer impurity.