TSV Semiconductor Package Sub-Stack Direct Connection
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Solution Overview
Problem
The challenge in semiconductor packaging lies in achieving high reliability and reducing defects during the stacking of semiconductor chips with through substrate vias (TSVs), as existing methods often result in thermal/physical damage and high defect rates due to repetitive high-temperature processes and the difficulty in providing reliable electrical connections between chips.
Innovation Solution
The method involves creating sub-package units with vertically stacked semiconductor chips, each including TSVs, and performing a reflow process to directly connect these units without a package substrate, thereby reducing the number of high-temperature processes and screening out defective units before stacking, ensuring reliable electrical connections and improved yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor chips are stacked using existing methods with repetitive high-temperature processes, then electrical connections between chips can be achieved, but thermal/physical damage occurs and defect rates increase
Solution Approach 1:
The patent applies preliminary action by performing the reflow process to create solder bumps on the TSVs before the stacking process. This preliminary preparation of connection structures allows subsequent stacking to occur at lower temperatures, avoiding repeated high-temperature exposure that causes thermal damage. The solder bumps are formed in advance and then used for direct connection during stacking, eliminating the need for repetitive high-temperature processes.
2Reliability
If repetitive high-temperature processes are used to create electrical connections between stacked chips, then connections can be established, but the number of defects increases
Solution Approach 1:
The patent performs preliminary formation of solder bumps on TSVs through a reflow process before stacking. This preliminary action ensures that connection structures are pre-established with proper metallurgical bonds, allowing subsequent stacking to occur at lower temperatures. The preliminary reflow process creates robust solder joints that are less susceptible to defects during stacking, thereby improving yield.
Solution Approach 2:
The patent changes the temperature parameter profile by replacing repetitive high-temperature processes with a single preliminary high-temperature reflow followed by low-temperature stacking. This parameter change from repeated high-temperature cycles to one high-temperature step plus low-temperature steps reduces thermal stress and defect formation while maintaining electrical connection reliability.
3Object-affected harmful factors
If sub-package units are directly connected without a package substrate, then the number of high-temperature processes is reduced, but ensuring reliable electrical connections becomes more challenging
Solution Approach 1:
The patent applies local quality by creating solder bumps specifically on the TSVs at the locations where direct contact is needed between sub-package units. This localized metallurgical preparation ensures that the critical connection points have enhanced bonding capability. The solder bumps provide locally optimized electrical and mechanical connections, enabling reliable direct stacking without package substrate while minimizing overall thermal exposure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of semiconductor packages by minimizing thermal/physical damage and reducing defect rates, allowing for efficient and reliable electrical connections between chips, while also improving the yield of usable semiconductor chips.
Implementation Method 1
performing a reflow process to directly electrically connect the first sub-package unit to the second sub-package unit
Data Source
AI summary
A method of manufacturing a semiconductor package includes forming at least two partial package chip stacks, each partial package chip stack including at least two semiconductor chips each including a plurality of through substrate vias (TSVs), and including a first mold layer surrounding side surfaces of the at least two semiconductor chips, and sequentially mounting the at least two partial package chip stacks on a package substrate in a direction vertical to a top surface of the package substrate, such that the at least two partial package chip stacks include a first partial package chip stack and a second partial package chip stack directly connected to the first partial package chip stack.