TSV Substrate Semiconductor Package Mounting
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Solution Overview
Problem
Existing semiconductor packages face challenges in minimizing space for vertical electrical interconnects, leading to increased package height and manufacturing costs due to the use of stacked semiconductor die with vertical interconnects.
Innovation Solution
The method involves forming a through silicon via (TSV) substrate and mounting semiconductor die on opposite sides of the TSV substrate, using conductive vias or bumps for interconnects, and encapsulating with a material to reduce package height and enhance interconnect efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stacked semiconductor die with vertical interconnects are used, then electrical connection between die is achieved, but package height increases and manufacturing cost increases
Solution Approach 1:
The patent transitions from vertical stacking to a planar arrangement where semiconductor die are mounted on opposite sides of a substrate. This dimensional change eliminates the need for vertical interconnects through the encapsulant, reducing package height while maintaining electrical connectivity through the substrate.
Solution Approach 2:
The substrate acts as an intermediary element that provides electrical connection between semiconductor die mounted on opposite sides. Instead of vertical interconnects passing through encapsulant, the substrate serves as the mediating structure for electrical pathways, reducing the need for complex vertical bonding structures.
2Reliability
If stacked semiconductor die with vertical interconnects are used, then electrical connection between die is achieved, but manufacturing cost increases
Solution Approach 1:
By arranging die on opposite sides of a substrate rather than stacking vertically, the patent simplifies the interconnection architecture. This eliminates complex vertical bonding processes and reduces manufacturing steps, thereby lowering production costs while maintaining reliable electrical connections.
Solution Approach 2:
The substrate serves as a cost-effective intermediary that provides electrical interconnection without requiring expensive vertical interconnect structures. This approach simplifies the manufacturing process and reduces material costs associated with complex vertical bonding and encapsulant routing.
3Reliability
If conventional packaging with encapsulant is used, then semiconductor die are protected, but space for vertical interconnects increases package footprint
Solution Approach 1:
The patent arranges semiconductor die on opposite sides of a substrate in a planar configuration rather than stacking them vertically. This dimensional reorganization eliminates the need for vertical interconnects within the encapsulant volume, reducing the package footprint while maintaining protective encapsulation.
Data Source
AI summary
A semiconductor device includes a wafer level substrate having a plurality of first conductive vias formed through the wafer level substrate. A first semiconductor die is mounted to the wafer level substrate. A first surface of the first semiconductor die includes contact pads oriented toward a first surface of the wafer level substrate. A first encapsulant is deposited over the first semiconductor die. A second semiconductor die is mounted to the wafer level substrate. A first surface of the second semiconductor die includes contact pads oriented toward a second surface of the wafer level substrate opposite the first surface of the wafer level substrate. A second encapsulant is deposited over the second semiconductor die. A plurality of bumps is formed over the plurality of first conductive vias. A second conductive via can be formed through the first encapsulant and connected to the first conductive via. The semiconductor packages are stackable.